GB1488433A - Dpsk modulator - Google Patents

Abstract

1488433 Data transmission; DPSK modulator; waveform generation INTERNATIONAL BUSINESS MACHINES CORP 21 Aug 1975 [21 Nov 1974] 34730/75 Headings H4P and H3H In a known arrangement in which sinusoidal waves are formed by directly computing vector angles # digitally, performing, by look up table of values, phase to amplitude translation which are then digit to analogue converted into sinusoids, and comprising a memory (11) (see Fig. 1, not shown) containing values ##0, ##1 representangular increments of two waves 0, 1 corresponding to binary levels 0, 1, the levels setting a switch (14) passing the values through a gate (15) to one input of an adder (17) working in conjunction with a circulatory incrementing register (18) (see sawtooth form of Fig. 1B, not shown) the output from 17 being converted from digital angle #(t) by ROM table (18) to digital amplitude sin #(t) which is applied to d/a converter (20) supplying its output to a filter (21) such known arrangement is adapted to provide DPSK signals in which band width and filter requirements are reduced and may be further reduced by smoothed transitions on binary level change. In particular the memory is expanded to include movements of fractional band time #T which are accumulated successively during continuous clock cycles. A clock of sampling frequency fs has three 90 degree spaced outputs plus (optionally) two in the 4th quadrant applied to address generator 31-1 together with three high order bits from buffer 32-1. For twinplex four phase modulation, binary input bit D1 specifies phase magnitude by selecting with other inputs to 31- 1 addresses from ROM 33-1 which are applied sequentially to adder/subtracter 34-1 acting in conjunction with circulatory feedback parallel incrementing registers 36-1, 37-1. Content of 36-1 is added to #T addresses from 33-1 during clock times Cl and then reinserted in 36-1 which addition is passed in turn to buffer 32-1 in manner described more fully in connection with Fig. 5 (not shown). During C2 time, 37-1 operates similarly with ## addresses. This is repeated during C3 time but 34-1 adds/subtracts depending on sign of data bit DO i.e. a 1 bit causes addition and conversely. During C4 time, content of register 37-1 is added to address of 33-1 and passed through a #/sin # ROM 41-1 to a buffer 45 under control of read/write/clear circuit 46 (which responds to clock pulses C4, C5, C1): content of 37-1 is not altered during C4 time. During C5 time, address from 33-1 is subtracted from 37-1 as specified by 38-1 and output is applied through 0/sin # converter 41-1 to adder 47, the other input receiving buffer 45 content. Output of 47 is inserted into register 42-1 and on trailing edge of C5 is applied to a d/a converter 43-1 having an output through filter 44-1 which may be of R-C type. The add/subtract control 38-1 comprising OR's 48, 49 plus AND 50 provides the following relationships: The arrangement provides Œ45 or Œ135 degrees DPSK for various combinations of D0, D1 inputs. Abrupt transitions between phases may be reduced (together with the band width) by introducing some amplitude modulation, by known technique of using two phase modulated carriers each with envelope modulation, phase changes being made when the envelope of one carrier is zero. This is done in C3 time when #(t) address is changed by ##(t) and during C4, C5 times address is changed by angle Œ#0(T), which generate a smoothed phase transition during a baud time (see Figs. 4A-4C, not shown) when added to content of buffer 45 by adder 47 output being inserted in 42-1. If a higher order of phase changes, e.g. 8 phase is required, the memory 33-1 addresses will need to be expanded accordingly. Where low baud rates are used or smooth transition is not required, processing steps during C4, C5 clock times may be eliminated. The arrangement may perform amplitude modulation by suppression of the C3 pulse and hence the processing steps occurring therein. The arrangement described may be modified to provide FSK signals also multi frequency signals either separately or in combination (see Fig. 10, not shown) aspects of which are claimed in copending divided Specifications 1,488,434 and 1,488,435.