GB1485183A - Integrated circuit devices and their fabrication - Google Patents

Abstract

1485183 Semi-conductor devices WESTERN ELECTRIC CO Inc 10 Jan 1975 [14 Jan 1974] 1031/75 Heading H1K In the manufacture of an integrated circuit a mesa portion of a semi-conductor body is laterally isolated by inset oxide 16a, 166, 16c, a first patterned metallization level 17, 18, 19 is provided having parts which overlap the inset oxide 16 and the isolated portion 14, an apertured dielectric mask 20a, 20b, 20c is deposited over the surface and impurities are introduced into a region 21 of the isolated portion defined by a masking layer constituted by the combination of the first level metallization 17-19, the inset oxide 16 and the dielectric mask 20. Preferably a second patterned level of metallization is subsequently deposited on the dielectric mask 20 to contact the region 21 and areas of the first metallization level exposed through other openings in the mask 20. In the manufacture of an integrated circuit containing an NPN transistor the semi-conductor body comprises a P-type B doped Si substrate 11 having an N+ As or Sb diffused surface zone 13 which is buried beneath a P- type epitaxial layer. Inset oxide 16a, 16b, 16c is formed by selective anisotropic etching followed by oxidation, to laterally isolate portions 14, 15 of the epitaxial layer as shown. The portion 15 is converted to N+-type conductivity by diffusion or ion implantation of P. The first metallization level 17, 18, 19, e.g. of Al, Au, Si or W, is applied and selectively covered with the dielectric mask 20, which may be a silicon nitride-silicon oxide composite. The N+-type emitter region 21 is formed by As diffusion or ion implantation followed by a low temperature anneal and finally, a second metallization level is formed, contacting the emitter region 21 and exposed areas 17, 19 of the first level.