GB1468988A - Simulation system - Google Patents

Abstract

1468988 Simulation INTERNATIONAL STANDARD ELECTRIC CORP 10 Dec 1974 [28 Dec 1973] 53353/74 Heading G4A [Also in Division H4] A data processing system includes a system computer CPa programmed to control a telecommunications switching network SN, a simulation computer CPd arranged to simulate the activity of the network under a traffic load, and an interface between the computers, the arrangement being such that when the time of occurrence of an event has to be determined the system computer is programmed to halt and the simulation computer is programmed to record the time of the halt, halt instructions being provided in the system computer program for at least some of the events at points where a halt would not be made if the system computer were controlling the network SN. The duration of a program, e.g. a program which searches for a free path in network SN, is measured by replacing the first instruction of the program and the first instruction following the program by multiple execute instructions see Specification 1,301,417 each of which controls the execution of a halt instruction and the replaced instruction of the program. A stop detector DS detects the halt instruction to produce signal AR to reset MA and block gate pt. The system computer CPa operates in response to clock pulses supplied via gate pt and is thus stopped. A counter C1G, repeatedly decremented to zero by the clock pulses, records the actual operating time of CPa (as opposed to time spent monitoring and timing the operation of CPa &c.) the signal ZRT serving to indicate that the counter contents have been decremented to zero, to reset flip-flop MA to block gate pt and thus stop CPa and the counter C1G, to increment a field in memory M to update an elapsed-time record, and to reload counter C1G, and to set flip-flop MA. In response to the detection of the halt the current elapsed time record in memory M is copied into a further memory field, the contents of counter C1G are read, and thus the start time of the path search program is calculated. Flip-flop MA is then set to restart computer CPa, which then executes the path search program, and to restart counter C1G. Any input/output instructions in the program are detected at DT to stop computer CPa and record their time of occurrence as above. Following execution of the last instruction of the path search program a further multiple execute instruction including a halt instruction and the first instruction following the program is executed to record, in the same way as above, the end time of the program. Thus by subtraction the actual duration of the program may be established and printed. During simulation computer CPa operates on data in memory M simulating the activity of the switching network rather than on the network itself.