GB1461943A - Semi-conductor devices - Google Patents

Abstract

1461943 Semi-conductor devices RAYTHEON CO 1 Feb 1974 [21 Feb 1973] 4821/74 Heading H1K Adjacent elements in a semi-conductor integrated circuit are isolated by removing Si from grooves 16 extending through a semiconductor Si layer 12 supported on a substrate 10, chemically reacting the walls of the grooves to form an insulating layer 26, depositing over the surface further insulating material 29 at temperatures not exceeding 1200‹ C. so as to fill the grooves, removing the further insulating material 29 down to the surface so as to leave the grooves filled and to form a flat continuous surface, and forming over the continuous surface a pattern of mutually insulated conductors 48 insulated from the surface by an intervening insulating layer 30 except at apertures through this layer where the conductors make contact with regions of the semi-conductor elements. All steps subsequent to, and including, the deposition of the further insulating material 29 are performed at temperatures not exceeding 1200‹ C., and preferably at below the plasticity temperature of Si, which is stated to be about 1050‹ C. P-type Si substrate 10 has an epitaxial layer 12 formed thereon in which the required semi-conductor elements, e.g. transistors and resistors, are formed. By appropriate selection of the crystallographic orientation of the Si body, V-shaped grooves 16 are anisotropically etched through the epitaxial layer 12. A multilayer insulating region is formed over the body 10, comprising a first low-impurity silicon dioxide layer 26 formed by thermal oxidation at 700-1100‹ C. and 300-3000 Angstroms thick, a second layer 28 of silicon nitride 1500 Angstroms thick and a layer 29 of high impurity silicon dioxide at least one micron thicker than the depth of the grooves 16. This layer 29 is formed by chemical vapour deposition at 300-1000‹ C. from an atmosphere of phosphene or diborane and silane in a carrier and an oxygen source. The resultant silicon dioxide deposit has an impurity concentration of 1- 50% enabling it to be heated to its softening point to flow evenly across the wafer surface without exceeding 1050‹ C. The wafer is then etched to remove layer 29 down to the nitride layer 28, but leaving the grooves 16 filled with material 29. Conventional techniques are then employed to form the respective electrode connections over further apertured insulating layer 30. The method may be employed in fabricating the integrated circuit memory cell arrangement described in Specification 1,383,893.