GB1457030A - Data processing system - Google Patents

Abstract

1457030 Data processing system INTERNATIONAL STANDARD ELECTRIC CORP 23 May 1974 [29 May 1973] 23064/74 Heading G4A In a data processing system comprising a plurality of memory modules, at least one of which is normally in a standby module, and associated memory control units, a plurality of computer modules connected to respective inputs of each of the control units access the memories by addressing the memory control units and each control unit has an associated reconfiguration unit storing the address of its associated control unit and data indicating which (if any) of its inputs are blocked, each reconfiguration unit being arranged such that any one of the computer modules can access and modify its stored address and blocking data, e.g. in order to replace a faulty memory module by the standby module. As described two computer modules 1A, 1B access three memory modules (not shown) via respective memory control units (only one, 2A, shown) each of which has an associated reconfiguration unit (only one, 3A, shown). The address to which the memory control unit responds is stored in register R1 and the data indicative of blocked inputs in register R2 in the reconfiguration unit. Either computer may load, modify, or read registers R1, R2 by sending the address of a reconfiguration unit to the units where it is compared in comparator 6 with a wired in address. The priority circuit 7 in the selected unit issues control signals to enable the accessing computer, or in the case where both computers make simultaneous access requests, a predetermined one of the computers to send address or blocking data via line (E)D1 to registers R1, R2, e.g. in order to replace a faulty memory and associated memory control unit by the standby memory and associated memory control unit, to read via gates Q1, Q<SP>1</SP>1, ... Qn, Q<SP>1</SP>n the contents of registers R1, R2, or to load registers R1, R2 with signals indicative of the states of a group of preset switches 12, the last procedure being used initially to set up the system. The reconfiguration unit also sends acknowledgement signals to the computers indicating that an access is being honoured or not, in the latter case e.g. due to an access conflict (see priority circuit 7 above). A unit 13 is also provided to load register R2 with status data, e.g. representing a parity fault in the reconfiguration unit address issued by the accessing computer, or a fault detected in the associated memory control unit.