GB1445855A - Apparatus for measuring the pitch period of the basic sounds of speech - Google Patents

Abstract

1445855 Pitch extractors for vocoders J F ZURCHER 16 Nov 1973 [16 Nov 1972] 53206/73 Heading H4R In a pitch extractor (for a vocoder) in which major peaks of a speech waveforrn are detected to provide marker pulses whose spacing defines a nominal pitch period, pulses occurring at less than a predetermined minimum time after the preceding pulse are cancelled but not twice in succession, the intervals defined by non-cancelled pulses and falling within tolerance limits relative to the preceding interval are stored, any interval falling outside the tolerance limits of the preceding interval being replaced by that preceding interval but not twice in succession. The stored intervals represent pitch periods. As a refinement those periods longer than a predetermined value are halved. A voiced/unvoiced decision circuit compares the energies in the speech band below 700 Hz with that about 1500 Hz and confirms that the input is speech by means of a threshold detector to enable the peak detector, processor and storage circuits. The major peak selector (Fig. 2) operates in parallel on positive and negative peaks by amplifying 20, peak-sharpening 21 and impedance-matching 22 the input speech to comparator 28 receiving the direct signal U 1 and a signal U 2 derived from a minor peak cancelling circuit 23 and an integrator 25. The integrator is a two transistor RC storage type (Fig. 3, not shown) providing a slowly decaying signal U 2 whenever a peak is detected. Subsequent intersections of U 1 with U 2 change the state of the comparator to indicate a peak. To ensure that subsequent major peaks of U 1 intersect U 2 , a portion of U 2 is subtracted from U 1 by RC network 28 11 -28 13 . Detection of a peak provides an output which grounds the integrator input by switch 17, triggers flip-flops 27, 29 to give the marker pulse output for subsequent processing and feeds back to amplifier 20 to enhance peak detection. The voiced decision input P switches in a further resistor in the time constant circuit of integrator 25 to ensure more rapid decay of U 2 . The processor (Fig. 4, not shown) receives the voiced decision control signal P to trigger sawtooth generators (40 0 , 40 1 ) whose outputs are compared (41 0 and 42 1 , 42 2 ) with an alternated version of the maximum level reached by the sawtooth in the previous period determined by successive pulses j received from the peak detector. The comparators (42 0 , 42 1 ) only provide outputs if the current period under scrutiny is shorter than the preceding period by an amount determined by the attenuators of the sawtooth waveform, and the other comparator (42 2 ) when the current period is longer by a given amount than the preceding period. The comparator outputs, the unvoiced signal P and the pulses j are employed in logical circuits determining the relative lengths of successive periods and whether a preceding period has been cancelled or not to generate signals F 1 and F 2 controlling a storage circuit (Fig. 5, not shown). The contents of a clock counter (704) are transferred to a register (707) by the logical product F 1 x F 2 and the output fed to a decoder (710) which corrects the data in output register (711) when the decoder reaches a predetermined number. The counter contents are therefore transferred into register (707) only when the pulses F 1 , F 2 coincide and the time between two successive F 2 pulses is counted between two resets. The decoder (710) performs the optional divide-by-two of long periods.