GB1324088A - Automatic control apparatus for adjusting an analogue output in steps - Google Patents

Abstract

1324088 Analogue/digital converters UZINELE ELECTRO PUTERE CRAIOVO 24 July 1970 36112/70 Heading G4H In an analogue/digital converter system of the type in which a feedback signal is compared with the analogue input to derive an error signal mz, when me > Ur 2 a control circuit FSC c enables a main control register DCP under the control of a signal In and when me <Ur 2 a secondary control register DCS is enabled under the control of a signal 1m so that a large or small modification is made to the feedback signal. The direction of the modification is determined by a circuit FSC r in dependence on the sign of the error. The secondary control register DCS which is a binary counter receives both positive or negative directional signals Sc or Sm from the circuit FCS r and an enabling signal from circuit BSC c receiving the signals 1n and 1m. The main control register DCP is controlled via a circuit BSC r to which the signal from circuit BSO c is fed via diodes D4, D5 to generate a signal c or m in dependence on whether a direction signal Sc or Sm is generated. The register DCP is a reversible binary counter, the output from each is used to derive a stepped analogue feedback signal, one step has the significance of 2<SP>m</SP> times the smallest step in the analogue signal derived from register DCS which is a reversible counter deriving a stepped analogue output, the steps of which are in geometrical progression. A principal limiter LCP prevents operation of circuit GSR comparing the error signal with a reference level Ur 1 to determine whether balance has been reached when registers DCS and DCP are at their maximum and the feedback signal is too small or when the registers are at their minimum and the feedback signal is too large. A secondary limiter LCS cancels the signal to register DCP when it is at its maximum or zero so that whatever the magnitude of the error the register DCS is driven.