GB1307566A - Decoder for the high colour fidelity reproduction of a pal-encoded colour signal - Google Patents

Abstract

1307566 Television INTERNATIONAL STANDARD ELECTRIC CORP 12 May 1970 [16 May 1969] 22851/70 Heading H4F In PAL decoders wherein phase errors are cancelled by delaying the chrominance signal for one line period and adding it to and subtracting it from the undelayed signal to provide separated U and V signals on respective subcarriers, the hue is rendered correct at the expense of introducing an error in the saturation. To provide correct hue and saturation the chrominance signal 1 is demodulated at 2, 3, to give signals 29, 16, dependent only on amplitude and phase (with the PAL alternation removed) respectively, the phase signal is averaged over successive pairs of lines, 4, 5, and the signals 29 and 20 are fed to a converter 6. If the signal 16 is a linear function of the subcarrier phase angle, such as is obtained using the circuit of Fig. 3, circuit 5 may be a simple adder and circuit 6 may be one wherein an oscillator output is separately phase and amplitude modulated by signals 29 and 20 respectively, the resulting pair of carrier signals being used to synchronously demodulate each other at each of two relative phase angles for the two colour signals, Fig. 7 (not shown). Alternatively, Fig. 8, the output of an oscillator 15 is fed via a variable delay 26 controlled by the signal 20 to phase comparators 33 and 34 operating in quadrature and also directly connected to the oscillator so that they provide outputs corresponding to the sine and cosine of the phase angle, which are multiplied by the signal 29 at 35, 36 to give (R-Y) and (B - Y) outputs. In Fig. 3, the amplitude limited chrominance signal and the output of a reference subcarrier oscillator 10 are halved in frequency and used to trigger bi-stables 9, 12. One of the pulse edges from each circuit 9, 12 is used to trigger a bi-stable 13 providing a pulse width modulated output indicative of the chrominance phase angle. After passing through a PAL switch and filter 19, the output is a voltage substantially linearly related to the phase angle over a range of 720 degrees. In an alternative embodiment, Figs. 9, 10, the signal 16 is related to the phase angle # in the way shown. The chrominance signal 1 is limited 7 and passed to phase comparators 37, 38 to give outputs sin # and cos #. Harmonic generators 39 and 40 convert these outputs to signals linearly dependent on #, but only for intervals of Œ45 degrees about the values of # for which the respective sin and cos functions are equal to zero, i.e. in this range they have a transfer function #/sin #. The signals sin # and cos # also control a circuit 44 operating switches 41, 43 to give the output of Fig. 10. Because of the form of this signal a simple adder circuit 5 is insufficient. Instead, Fig. 11 (not shown), a circuit (50) compares the values and signs of the delayed and undelayed signals, e.g. # 1 and # 2 in Fig. 10 and operates a switch determining whether the delayed signal has a voltage + #V, zero or - #V superimposed thereon before being added to the undelayed signal. The arranged signal is supplied to a further circuit, Fig. 13 (not shown), comprising further switches controlled by the output of circuit 44 whereby signals in the various quadrants of Fig. 10 have a potential of Œ¢#V superimposed, and are inverted in two of the quadrants to afford outputs such as in Fig. 12c (and Fig. 12b, not shown) which are smoothed by harmonic generators to give outputs corresponding to cos # and sin #, e.g. curve U62. These are supplied to the circuits 35, 36, Fig. 8. The nature of the averaging process performed in the circuit of Fig. 11 is such as to give some distortion in the region X 1 , X 2 , since the averaged output thereof may be greater than #V/2 in this region. The delay device 4 may be a shift register, e.g. of 190 MOSFET in series switched at <SP>1</SP>/ 3 of the subcarrier frequency, Fig. 6 (not shown).