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GB1388629A - Bipolar to mos interface circuit - Google Patents

Bipolar to mos interface circuit

Info

Publication number
GB1388629A
GB1388629A GB2131972A GB2131972A GB1388629A GB 1388629 A GB1388629 A GB 1388629A GB 2131972 A GB2131972 A GB 2131972A GB 2131972 A GB2131972 A GB 2131972A GB 1388629 A GB1388629 A GB 1388629A
Authority
GB
United Kingdom
Prior art keywords
turn
gate
drain
source
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2131972A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsystems International Ltd
Original Assignee
Microsystems International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA116959A external-priority patent/CA918757A/en
Application filed by Microsystems International Ltd filed Critical Microsystems International Ltd
Priority claimed from CA218,493A external-priority patent/CA1057331A/en
Publication of GB1388629A publication Critical patent/GB1388629A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10P95/00—

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1388629 Bipolar-FET interface circuits MICROSYSTEMS INTERNATIONAL Ltd 8 May 1972 [29 June 1971 17 Jan 1972] 21319/72 Heading H3T [Also in Division H1] The necessary gate to source voltage required to turn on an inverting F.E.T. T1 is increased by feeding back the drain voltage to control a device such as a F.E.T. T2 connected between its gate and source. Thus the negative input voltage change must turn on T1 sufficiently hard to cause the potential at A to turn off T2, and permit T1 to be turned on completely. Also, when T1 is being turned off by a positive-going INPUT voltage, the drain A goes towards earth by virtue of impedance T3, so turning on T2 which takes T1 gate towards the source voltage V ss (e.g. +5v) and accelerates turn-off of T1. Gating F.E.T.'s T4, T5 are clock controlled to gate the input and output signals. The integrated circuit (Fig. 4, not shown) has the drain and source regions of the F.E.T.s formed in various p-diffused areas identified by the corresponding reference numerals (D1, S1, &c.). The gates (G1, &c.) are polysilicon deposits over the diffusions, and metallizations form the input, output and supply lines.
GB2131972A 1971-06-29 1972-05-08 Bipolar to mos interface circuit Expired GB1388629A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA116959A CA918757A (en) 1972-01-17 1971-06-29 Bipolar to mos interface circuit
US21849472A 1972-01-17 1972-01-17
CA218,493A CA1057331A (en) 1974-02-07 1975-01-23 Aspirated vehicle occupant restraint system

Publications (1)

Publication Number Publication Date
GB1388629A true GB1388629A (en) 1975-03-26

Family

ID=27161283

Family Applications (2)

Application Number Title Priority Date Filing Date
GB2131872A Expired GB1341334A (en) 1971-06-29 1972-05-08 Static bipolar to mos interface circuit
GB2131972A Expired GB1388629A (en) 1971-06-29 1972-05-08 Bipolar to mos interface circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB2131872A Expired GB1341334A (en) 1971-06-29 1972-05-08 Static bipolar to mos interface circuit

Country Status (3)

Country Link
DE (1) DE2231203A1 (en)
FR (1) FR2144361A5 (en)
GB (2) GB1341334A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759689B2 (en) * 1974-09-30 1982-12-16 Citizen Watch Co Ltd
DE3026040C2 (en) * 1980-07-09 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Switch with MOS-FET connected in series

Also Published As

Publication number Publication date
GB1341334A (en) 1973-12-19
FR2144361A5 (en) 1973-02-09
DE2231203A1 (en) 1973-01-25

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees