GB1380388A - Indication of change of position of parts of a mechanical system - Google Patents

Abstract

1380388 Indicating movement TRADE & INDUSTRY SECRETARY OF STATE FOR 23 Feb 1972 [23 Nov 1970] 55532/70 Heading G4H In a system for indicating movement using an A.C. resolver, the output of a resolver fed with reference phase signals is converted to pulses. Each pulse in the resulting output train is then compared in logic circuitry with the preceding pulse in the pulse train delayed by the period of the reference phase signal. One or more clock pulses appears at a first output when the pulse in the output train appears before the pulse in the delayed train or at a second output when the pulses arrive in the reverse order. The outputs are fed to the up and down inputs respectively of a counter; a change of count indicating movement of the A.C. resolver. As shown, a 10 kHz clock pulse generator 14 feeds dividers 18, 22 to provide a 1 kHz sine output from filter 26 and a 1 kHz cosine output from filter 42. These form the reference phase signals to resolver 32. The sine wave output of resolver 32, which is displaced in phase relative to the standards by an amount related to the position of input 48, is converted to a pulse train and fed to logic circuitry 60. 10 kHz clock pulses are also fed to the logic circuitry, which is shown in detail in Fig. 2. An input pulse from generator 56, sets flip-flop 62, enables AND gate 64 and passes a clock pulse to monostable 68 which resets flip-flop 62. This synchronizes the input pulses with clock pulses. The pulses are then delayed 50 Ás (half the clock period) at 70 to prevent gating problems. The pulse is fed along line 72 and sets flip-flop 74, enabling AND gate 76 and supplying divider 78 with clock pulses. 500 Ás later the output of divider 78 resets flip-flop 74 and sets flip-flop 80. The thusenabled AND gate 82 passes clock pulses to divider 84, and after another 500 Ás an output is passed from divider 84 to delay 86 where another 50 Ás delay occurs. The signal on line 88 is thus the input signal on line 72 delayed by 1 ms.; the period of the reference phase signal. Line 72 is also applied to the set input of flip-flop 90 and the reset input of flip-flop 98 and line 88 to the other inputs of these flip-flops. When a pulse on line 72 arrives before a pulse on line 88, AND gate 92 is enabled and clock pulses pass on line 94 to the up input of counter 96 during the difference period. When the pulses arrive in the opposite order, AND gate 100 is enabled and the output is on line 102 to the down input of counter 102.