GB1372414A - Semiconductor memory device arrangements - Google Patents
Semiconductor memory device arrangementsInfo
- Publication number
- GB1372414A GB1372414A GB3545471A GB3545471A GB1372414A GB 1372414 A GB1372414 A GB 1372414A GB 3545471 A GB3545471 A GB 3545471A GB 3545471 A GB3545471 A GB 3545471A GB 1372414 A GB1372414 A GB 1372414A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- conducting
- memory device
- render
- long enough
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 150000004770 chalcogenides Chemical class 0.000 abstract 1
- 238000013500 data storage Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Read Only Memory (AREA)
Abstract
1372414 Data storage MARCONI CO Ltd 26 Nov 1971 [28 July 1971] 35454/71 Heading G4C A memory device of the kind comprising an amorphous layer of semi-conducting glass chalcogenide is driven into its conductive state by a first pulse 7 and the conductive state is fixed by a second pulse 6; the first pulse applies a voltage above the theshold value V T for a short time long enough to render the device conducting but not long enough to make the conducting state permanent while the second pulse maintains a smaller current through the device for a longer period such that the device remains conducting after the pulse ends and until a further pulse is applied to render it non conducting. In a two dimensional array of devices (Fig. 7, not shown) the two pulse forms shown in Fig. 8 can be applied by horizontal and vertical lines; only the device at the junction of the two selected lines is then rendered conductive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB3545471A GB1372414A (en) | 1971-11-26 | 1971-11-26 | Semiconductor memory device arrangements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB3545471A GB1372414A (en) | 1971-11-26 | 1971-11-26 | Semiconductor memory device arrangements |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1372414A true GB1372414A (en) | 1974-10-30 |
Family
ID=10377922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB3545471A Expired GB1372414A (en) | 1971-11-26 | 1971-11-26 | Semiconductor memory device arrangements |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1372414A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4225946A (en) * | 1979-01-24 | 1980-09-30 | Harris Corporation | Multilevel erase pulse for amorphous memory devices |
| US4228524A (en) * | 1979-01-24 | 1980-10-14 | Harris Corporation | Multilevel sequence of erase pulses for amorphous memory devices |
| US6687153B2 (en) | 2001-06-29 | 2004-02-03 | Ovonyx, Inc. | Programming a phase-change material memory |
| WO2004025659A1 (en) | 2002-09-11 | 2004-03-25 | Ovonyx, Inc. | Programming a phase-change material memory |
| WO2004055828A3 (en) * | 2002-12-13 | 2004-11-04 | Ovonyx Inc | Memory and access devices |
| EP1196924A4 (en) * | 1999-06-22 | 2005-12-07 | Ovonyx Inc | Method of programming phase-change memory element |
-
1971
- 1971-11-26 GB GB3545471A patent/GB1372414A/en not_active Expired
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4225946A (en) * | 1979-01-24 | 1980-09-30 | Harris Corporation | Multilevel erase pulse for amorphous memory devices |
| US4228524A (en) * | 1979-01-24 | 1980-10-14 | Harris Corporation | Multilevel sequence of erase pulses for amorphous memory devices |
| EP1196924A4 (en) * | 1999-06-22 | 2005-12-07 | Ovonyx Inc | Method of programming phase-change memory element |
| US6687153B2 (en) | 2001-06-29 | 2004-02-03 | Ovonyx, Inc. | Programming a phase-change material memory |
| WO2004025659A1 (en) | 2002-09-11 | 2004-03-25 | Ovonyx, Inc. | Programming a phase-change material memory |
| GB2407707A (en) * | 2002-09-11 | 2005-05-04 | Ovonyx Inc | Programming a phase-change material memory |
| CN100449647C (en) * | 2002-09-11 | 2009-01-07 | 奥翁尼克斯公司 | Program Phase Change Material Memory |
| DE10297786B4 (en) * | 2002-09-11 | 2012-11-08 | Ovonyx Inc. | Programming a phase change material memory |
| WO2004055828A3 (en) * | 2002-12-13 | 2004-11-04 | Ovonyx Inc | Memory and access devices |
| CN100552812C (en) * | 2002-12-13 | 2009-10-21 | 奥沃尼克斯股份有限公司 | Storage device and access device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |