GB1340653A - Fet read-only storage matrix - Google Patents

Abstract

1340653 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [5 June 1971] 24345/72 Heading H1K A read-only FET memory matrix includes, in an N (or P) type substrate 1, a plurality of parallel P (N) type bit line strips 2, 3 constituting common source regions for rows of memory cells whose drain regions comprise discrete P (N) type regions 7, 9, and parallel metal word line strips 5 perpendicular to the bit line strips 2, 3 and constituting the gate electrodes of the memory cells. The insulating layer 10 isolating the strips 5 from the substrate 1 and constituting the gate insulation of each wall is thinnest where it overlies the discrete P (N) type drain regions 7, 9 at 12, 14. This allows, for selected cells, a single 'write' process involving the application, between the selected word and bit lines, of a potential sufficient to induce breakdown of the thin portion 12 or 14 of the insulating layer 10, thereby to short the selected drain region 7 or 9 to the metal strip 5 and to charge the memory state of the cell. The channels of the individual cells may be restricted to the areas 16, 18 either by making the insulation 10 relatively thin over these areas, as shown, or by providing heavily-doped N<SP>+</SP> (P<SP>+</SP>) type zones elsewhere in the surface of the substrate 1. The "write" and "read" processes are described in detail, as in the conventional planar process used to manufacture the matrix.