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GB1227988A - - Google Patents

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Publication number
GB1227988A
GB1227988A GB1227988DA GB1227988A GB 1227988 A GB1227988 A GB 1227988A GB 1227988D A GB1227988D A GB 1227988DA GB 1227988 A GB1227988 A GB 1227988A
Authority
GB
United Kingdom
Prior art keywords
counter
state
period
reset
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1227988A publication Critical patent/GB1227988A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

1,227,988. Digital transmission systems. INTERNATIONAL COMPUTERS Ltd. 12 May, 1969 [6 June, 1968], No. 26979/68. Heading H4P. To reduce the likelihood of synchronizing a clock pulse circuit on spurious noise pulses which accompany received digital data signals the circuit includes a counter which cycles at a rate nominally equal to the digit rate and which can be reset by a received signal only during a period defined by two states of the counter. As described the counter has a 16-state cycle S0-S15 and the said period lasts from the beginning of state S15 until the end of state S1. The received signal D 0 (binary data and noise) is sampled at gate 11 by pulses Y 1 derived from state S7 of the counter 13 and occurring at about the centre of each bit. Each negativegoing transistion in signal D 0 causes monostable T 1 to produce a pulse which resets counter 13 to state S0 if gate 14 is enabled. The period during which gate 14 is enabled is determined by bi-stable N 1 which is set to one state at the end of counter state S14 and is reset at the end of S1. Any transitions occurring outside this period thus can not reset the counter. Counter 13 is set to zero at the start of transmission by bi-stable M 1 , triggered when, for example, a start character has been received.
GB1227988D 1968-06-06 1968-06-06 Expired GB1227988A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2697968 1968-06-06

Publications (1)

Publication Number Publication Date
GB1227988A true GB1227988A (en) 1971-04-15

Family

ID=10252208

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1227988D Expired GB1227988A (en) 1968-06-06 1968-06-06

Country Status (1)

Country Link
GB (1) GB1227988A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076008A1 (en) * 1981-09-29 1983-04-06 Koninklijke Philips Electronics N.V. A receiver for FFSK modulated data signals
GB2191068A (en) * 1986-05-28 1987-12-02 Marconi Instruments Ltd Electrical apparatus for extracting clock signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076008A1 (en) * 1981-09-29 1983-04-06 Koninklijke Philips Electronics N.V. A receiver for FFSK modulated data signals
GB2191068A (en) * 1986-05-28 1987-12-02 Marconi Instruments Ltd Electrical apparatus for extracting clock signals

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee