GB1224531A - Digital clutter rejection in a pulse radar system - Google Patents

Abstract

1,224,531. Pulse radar. HUGHES AIRCRAFT CO. 24 June, 1968, No. 30086/68. Heading H4D. In a system for processing radar video received as a plurality of signal sweeps in response to a selected number of transmitted pulses an encoder 20, Fig. 2, converts the radar video into digital signals, a digital cancellation stage 24 includes at least one cancellation unit 32a, 32b, Fig. 4, and a digital data processor 30 incorporates a plurality of means for storing the output of the cancellation stage representing radar video from selected radar repetition periods and incorporates means for serially reading out the digital signals from each radar range received during each of the selected radar repetition periods. Only one Doppler filter bank is then necessary, unlike prior art (Fig. 1, not shown) which has a filter bank for each radar range "bin". The invention affords clutter rejection. High or low pulse repetition rates may be utilized. Timing of the transmitted pulses, of the sampling clock pulses to encoder 20, of the sweep selection gate 26 and of processor 30, is afforded from a control circuit 22. In the embodiment encoder 20 affords a series of digital multi-bit produced at a sampling frequency f s which is at least (1/d) where d is the transmitted pulse width. The cancellation stage has two cancellers in series, Fig. 4; if the signal from encoder is M bits, a set of M parallel delay (e.g. magnetostrictive) lines are provided in block 32b but it is stated that (a) less than M bits, and hence fewer delay lines, are needed in unit 34a and (b) the output from unit 34 need be even less bits, e.g. if M=8, there need only be four bit signals fed into gate 26, Fig. 2. Gate 26 selects the number of sweeps P in a given number N thereof to minimize the effect of clutter frequency spectrum spreading due to a finite value of N; the theory is explained, Fig. 5 (not shown). Processor 30, Fig. 6, comprises for each of the four bits a number P of digitized sweep delay lines 61-65 and a shift register 66, the outputs of all shift registers being fed to a decoder 70 which is followed by a single bank of Doppler filters. Weighting by unit 72 of the amplitudes of signals may be added to further minimize spreading of the clutter spectrum into the Doppler filters.