GB1202515A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- GB1202515A GB1202515A GB3706/69A GB370669A GB1202515A GB 1202515 A GB1202515 A GB 1202515A GB 3706/69 A GB3706/69 A GB 3706/69A GB 370669 A GB370669 A GB 370669A GB 1202515 A GB1202515 A GB 1202515A
- Authority
- GB
- United Kingdom
- Prior art keywords
- insulating layer
- metal layer
- layer
- substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H10W74/40—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H10W72/90—
-
- H10W72/5363—
-
- H10W72/59—
Landscapes
- Electrodes Of Semiconductors (AREA)
- Local Oxidation Of Silicon (AREA)
- Formation Of Insulating Films (AREA)
Abstract
1,202,515. Semi-conductor devices. HITACHI Ltd. 22 Jan., 1969 [24 Jan., 1968; 2 Feb., 19681, No. 3706/69. Heading H1K. In a planar semi-conductor device wherein the PN junctions all terminate on a single surface, this surface being covered by an insulating layer, a second insulating layer is formed over the first insulating layer and a metal layer is formed on the surface of this second insulating layer. the two extra layers providing added protection against moisture or impurity ions penetrating to the semi-conductor surface. The invention may be applied to an IGFET having source 2 and drain 3 regions in a substrate 1, source, drain and gate electrodes 6, 7 and 8, respectively, and an insulating layer 4, 5, which extends over the whole surface of the device. In this embodiment the second insulating layer 9 carrying the metal layer 10 overlies the entire surface area of the source and drain regions and overlaps this area to cover at least the area of extent of the depletion layer which occurs with reverse voltage in use. The metal layer 10 may be in contact with the substrate through an aperture in the insulating layers. The substrate is of silicon and the insulating layer 4, 5 is of silicon oxide. The second insulating layer 9 is of silicon oxide, silicon nitride, aluminium oxide or a resin or plastics material. The metal layer 10 is of aluminium, gold or silver, and the electrodes 6, 7 and 8 are of aluminium, titanium, molybdenum, chromium or platinum. Such IGFETs may be used in integrated circuits, Fig. 11, not shown. The invention may also be applied to a bipolar transistor, Figs. 15-17, not shown, and plastics encapsulated transistors, Fig. 24, not shown.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP376268 | 1968-01-24 | ||
| JP1968006635U JPS4620485Y1 (en) | 1968-02-02 | 1968-02-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1202515A true GB1202515A (en) | 1970-08-19 |
Family
ID=26337401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB3706/69A Expired GB1202515A (en) | 1968-01-24 | 1969-01-22 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE1903342B2 (en) |
| FR (1) | FR2000657A1 (en) |
| GB (1) | GB1202515A (en) |
| NL (1) | NL6901059A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511396B1 (en) * | 1970-09-07 | 1976-01-16 | ||
| DE2503864A1 (en) * | 1975-01-30 | 1976-08-05 | Siemens Ag | IGFET semiconductor component with doped region substrate - has semiconductor layer on insulating film with differently doped drain and source regions |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3767981A (en) * | 1971-06-04 | 1973-10-23 | Signetics Corp | High voltage planar diode structure and method |
| US3961358A (en) * | 1973-02-21 | 1976-06-01 | Rca Corporation | Leakage current prevention in semiconductor integrated circuit devices |
| GB2097581A (en) * | 1981-04-24 | 1982-11-03 | Hitachi Ltd | Shielding semiconductor integrated circuit devices from light |
| JPS5984542A (en) * | 1982-11-08 | 1984-05-16 | Nec Corp | High-frequency semiconductor integrated circuit |
| US5432127A (en) * | 1989-06-30 | 1995-07-11 | Texas Instruments Incorporated | Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads |
| US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1419107A (en) * | 1964-02-04 | 1965-11-26 | Fairchild Camera Instr Co | Equipotential adjustment of the surface characteristics of a semiconductor |
-
1969
- 1969-01-22 NL NL6901059A patent/NL6901059A/xx unknown
- 1969-01-22 GB GB3706/69A patent/GB1202515A/en not_active Expired
- 1969-01-23 DE DE19691903342 patent/DE1903342B2/en active Pending
- 1969-01-23 FR FR6901266A patent/FR2000657A1/fr not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511396B1 (en) * | 1970-09-07 | 1976-01-16 | ||
| DE2503864A1 (en) * | 1975-01-30 | 1976-08-05 | Siemens Ag | IGFET semiconductor component with doped region substrate - has semiconductor layer on insulating film with differently doped drain and source regions |
Also Published As
| Publication number | Publication date |
|---|---|
| DE1903342A1 (en) | 1969-09-11 |
| DE1903342B2 (en) | 1971-05-13 |
| NL6901059A (en) | 1969-07-28 |
| FR2000657A1 (en) | 1969-09-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |