GB1286737A - Multilevel conductive systems - Google Patents
Multilevel conductive systemsInfo
- Publication number
- GB1286737A GB1286737A GB47462/70A GB4746270A GB1286737A GB 1286737 A GB1286737 A GB 1286737A GB 47462/70 A GB47462/70 A GB 47462/70A GB 4746270 A GB4746270 A GB 4746270A GB 1286737 A GB1286737 A GB 1286737A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conductors
- channels
- silicon
- oct
- insulating layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H10W20/40—
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
1286737 Integrated circuits ITT INDUSSTRIES Inc 6 Oct 1970 [15 Oct 1969] 47462/70 Heading HlK In the manufacture of a multilayer connection system disposed on an integrated circuit semiconductor wafer the conductors are formed in channels so that their upper surfaces lie flush with the tops of respective insulating layers to avoid the strains which normally arise in such systems due to depositing material on uneven surfaces. In the described arrangements the wafer is of silicon, the insulating layers are alternately of silicon dioxide and nitride with either material next to the silicon, and the conductors are of gold. Each insulating layer is etched to form channels for the conductors, which are formed by depositing gold overall and then etching to confine it to the channels.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US86655569A | 1969-10-15 | 1969-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1286737A true GB1286737A (en) | 1972-08-23 |
Family
ID=25347860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB47462/70A Expired GB1286737A (en) | 1969-10-15 | 1970-10-06 | Multilevel conductive systems |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE2049908B2 (en) |
| FR (1) | FR2066013A5 (en) |
| GB (1) | GB1286737A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0101960A1 (en) * | 1982-07-30 | 1984-03-07 | Hitachi, Ltd. | Method of manufacturing a semiconductor device having a self-aligned gate electrode |
| US5063175A (en) * | 1986-09-30 | 1991-11-05 | North American Philips Corp., Signetics Division | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
| US5084414A (en) * | 1985-03-15 | 1992-01-28 | Hewlett-Packard Company | Metal interconnection system with a planar surface |
| EP0262719B1 (en) * | 1986-09-30 | 1993-12-15 | Koninklijke Philips Electronics N.V. | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4960870A (en) * | 1972-10-16 | 1974-06-13 | ||
| US3844831A (en) * | 1972-10-27 | 1974-10-29 | Ibm | Forming a compact multilevel interconnection metallurgy system for semi-conductor devices |
| US3985597A (en) * | 1975-05-01 | 1976-10-12 | International Business Machines Corporation | Process for forming passivated metal interconnection system with a planar surface |
| US4035276A (en) * | 1976-04-29 | 1977-07-12 | Ibm Corporation | Making coplanar layers of thin films |
| DE3228399A1 (en) * | 1982-07-29 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED CIRCUIT |
| JPS5982746A (en) * | 1982-11-04 | 1984-05-12 | Toshiba Corp | Electrode wiring method of semiconductor device |
-
1970
- 1970-10-06 GB GB47462/70A patent/GB1286737A/en not_active Expired
- 1970-10-10 DE DE19702049908 patent/DE2049908B2/en not_active Ceased
- 1970-10-15 FR FR7037272A patent/FR2066013A5/fr not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0101960A1 (en) * | 1982-07-30 | 1984-03-07 | Hitachi, Ltd. | Method of manufacturing a semiconductor device having a self-aligned gate electrode |
| US5084414A (en) * | 1985-03-15 | 1992-01-28 | Hewlett-Packard Company | Metal interconnection system with a planar surface |
| US5063175A (en) * | 1986-09-30 | 1991-11-05 | North American Philips Corp., Signetics Division | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
| EP0262719B1 (en) * | 1986-09-30 | 1993-12-15 | Koninklijke Philips Electronics N.V. | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2049908B2 (en) | 1976-03-25 |
| DE2049908A1 (en) | 1971-04-22 |
| FR2066013A5 (en) | 1971-08-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PLNP | Patent lapsed through nonpayment of renewal fees |