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GB1260468A - Improvements in or relating to the formation of connections on microelectronic circuits - Google Patents

Improvements in or relating to the formation of connections on microelectronic circuits

Info

Publication number
GB1260468A
GB1260468A GB15028/68A GB1502868A GB1260468A GB 1260468 A GB1260468 A GB 1260468A GB 15028/68 A GB15028/68 A GB 15028/68A GB 1502868 A GB1502868 A GB 1502868A GB 1260468 A GB1260468 A GB 1260468A
Authority
GB
United Kingdom
Prior art keywords
mask
conductors
pillars
pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB15028/68A
Inventor
Norman Davey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NAT RES DEV
National Research Development Corp UK
Original Assignee
NAT RES DEV
National Research Development Corp UK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NAT RES DEV, National Research Development Corp UK filed Critical NAT RES DEV
Priority to GB15028/68A priority Critical patent/GB1260468A/en
Publication of GB1260468A publication Critical patent/GB1260468A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H10W70/05
    • H10W70/098
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0382Continuously deformed conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10234Metallic balls
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

1,260,468. Welding by pressure. NATIONAL RESEARCH DEVELOPMENT CORP. 26 March, 1969 [28 March, 1968], No. 15028/68. Heading B3R. [Also in Divisions C1, H1 and H2] In forming connections to metallic conductors of a microelectronic circuit pattern on a substrate, an apertured mask is located over the pattern, metallic particles thicker than the mask are placed in apertures in the mask in contact with the conductors, the particles are pressed against the conductors to bond them thereto and the mask is removed to leave connection pillars bonded to the pattern. A substrate 1 of alumina has a pattern of conductors 2 formed thereon by screen printing or by vacuum deposition through a photo-resist mask, the conductors being at least surfaced with gold, and over the pattern a perforated mask 4 is held, gold spheres 8 being brushed over the mask to occupy the perforations. The spheres protrude above the mask which may be of foil not containing lead, e.g. aluminium or phosphor-bronze or plastics sheet and large perforations may be filled with several spheres side by side. With the substrate on a platen 6 a movable steel platen 7 is pressed on to the spheres to deform them to fill the perforations and pressure bond them to the conductors. The platens 6, 7 are preferably heated and the substrate may be heated to 150-250‹ C. The mask is peeled away leaving upstanding pillars on which inverted integrated circuit chips may be thermocompression bonded. An insulating layer may be formed on the substrate about the pillars before the chip bonding to protect the conductors by applying a colloidal suspension of powdered glass frit in a volatile liquid, e.g. isopropyl alcohol in ethyl acetate and heating to fuse the glass. Instead of mounting chips on the pillars which extend above the insulating layer, the pillars are ground to be flush with the layer and a further pattern of conductors is formed thereon. The process may be repeated to form a multilayer microelectronic circuit with interconnecting pillars. Instead of a glaze an epoxy resin insulating layer may be used possibly containing alumina particles or in a multilayer circuit a series of glazes of progressively lower fusion temperatures or a glaze containing refractory oxide particles may be used.
GB15028/68A 1968-03-28 1968-03-28 Improvements in or relating to the formation of connections on microelectronic circuits Expired GB1260468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB15028/68A GB1260468A (en) 1968-03-28 1968-03-28 Improvements in or relating to the formation of connections on microelectronic circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB15028/68A GB1260468A (en) 1968-03-28 1968-03-28 Improvements in or relating to the formation of connections on microelectronic circuits

Publications (1)

Publication Number Publication Date
GB1260468A true GB1260468A (en) 1972-01-19

Family

ID=10051786

Family Applications (1)

Application Number Title Priority Date Filing Date
GB15028/68A Expired GB1260468A (en) 1968-03-28 1968-03-28 Improvements in or relating to the formation of connections on microelectronic circuits

Country Status (1)

Country Link
GB (1) GB1260468A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268956A (en) * 1977-10-13 1981-05-26 Bunker Ramo Corporation Method of fabricating an interconnection cable
EP0267359A3 (en) * 1986-09-15 1989-04-26 International Business Machines Corporation Mask for depositing paste material
FR2622384A1 (en) * 1987-10-23 1989-04-28 Bbc Brown Boveri & Cie MULTI-LAYER THIN FILM CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF
EP0561620A3 (en) * 1992-03-19 1994-04-06 Hitachi Ltd
EP1348234A1 (en) * 2000-12-29 2003-10-01 Infineon Technologies AG A method and an arrangement for providing vias in printed circuit boards

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268956A (en) * 1977-10-13 1981-05-26 Bunker Ramo Corporation Method of fabricating an interconnection cable
EP0267359A3 (en) * 1986-09-15 1989-04-26 International Business Machines Corporation Mask for depositing paste material
FR2622384A1 (en) * 1987-10-23 1989-04-28 Bbc Brown Boveri & Cie MULTI-LAYER THIN FILM CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF
EP0561620A3 (en) * 1992-03-19 1994-04-06 Hitachi Ltd
US5497545A (en) * 1992-03-19 1996-03-12 Hitachi, Ltd. Method of making electrical connections in the manufacture of wiring sheet assemblies
EP1348234A1 (en) * 2000-12-29 2003-10-01 Infineon Technologies AG A method and an arrangement for providing vias in printed circuit boards

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Legal Events

Date Code Title Description
CSNS Application of which complete specification have been accepted and published, but patent is not sealed