GB1119574A - Programmable control device for analog computers - Google Patents

Abstract

1,119,574. Digitally programmed analogue computer. EUROPEAN ATOMIC ENERGY COMMUNITY (Euratom). 9 Sept., 1965 [14 Sept., 1964], No. 37505/64. Headings G4A and G4G. An analogue computer 1 (Fig. 1) comprising integrators 2, potentiometers 3, multipliers 4, and other computing elements has a patch panel 5 on which desired elementary interconnections may be set up manually. The integrators are capable of being set into operative modes comprising " compute ", " hold " and " initial condition " determined for each by control inputs emanating from a grouping matrix 6 (Fig. 2) controlling the integrators in three groups assuming a sequence of operation modes, each having " hold and " initial condition" control inputs 6a, 6b; the matrix outputs 6c, 6d constituting " hold and " initial condition " controls for integrators 2 which are connectible to inputs 6a, 6b by insertion of a suitably punched card 7 (Fig. 1) into a reader (not shown), or in response to switching controlled manually, or in response to an auxiliary digital computer (not shown). Digital group mode control signals from generators 8 (Fig. 3) are supplied to the integrator control matrix, and a patch panel 9 enables comparators 10, control delays 11, push-buttons 12, AND gates 13 to be manually interconnected in accordance with a required operational mode sequence programme. Fig. 3 shows a mode control generator with inputs 14, 15, 16 receiving signals determining " hold ", " compute " and " initial condition " modes over signal isolation diodes from the patch panel 9 and computing elements 10 to 13, while its outputs 17, 18 are connected to inputs 6a, 6b of the group matrix (Fig. 2) establishing " hold " and " initial condition " modes respectively. A positive pulse at input 14 operates relay K1 and pulses output 17 to " hold " mode. Relay contact b changes over to indicate the relevant mode, and contact a changes over to energize a patch panel contact for automatic plotter control, while contact c opens for single step control. A positive pulse at input 16 energizes output 18 to " initial condition " mode and operates relay K3. Relay contact a changes over to apply signal over diode CR5 to output 17, and holds for 3 mS after fall off of signal at output 18 to allow change from " initial condition " to " compute " without intervention of " hold " mode therebetween. Contact b in series with contact c for single step control also opens. Energization of relay K2 with output 17 closes contact b so that the relay holds energized for 100 mS and then releases, under control of charging RC network R 1 C 1 so that final results may be passed to recorder/indicators 19 or a digital computer over relay K5. Data may also be extracted by energizing K2 over push switch SW3. When a "compute" signal is received by input 15, diode CR8 transmits it to " a " contact of push switch SW1 and to integrator 28, which is operated to pulse all the groups in " compute " mode over contacts K3b and K1c to " hold " mode by energization of relay K4 and closure of K4a, so that push switch SW2 is operable to return all these groups to "compute" mode; thus push switches SW1, SW2 hold and release the " compute " mode. The patch panel 9 programming the group mode control (Figs. 6a, 6b, not shown) contains mode control-circuit inputs, five parallel outputs of an amplifying computer (Fig. 4, not shown), five parallel inputs and outputs of a delay circuit and five push switches for manual control. Contacts a of relay K1 are also brought out, and the panel may accommodate up to 10 groups. Interconnection of elements may be effected as desired. The sequence control delay circuit (Fig. 5, not shown) comprises five inputs connected to the input of a bi-stable flip-flop followed by a delay network, a gate, and a monostable pulse generator, and Figs. 7a to 7h (not shown) exemplify the control of an analogue computer circuit in response to a digital control from a punched card.