GB1162565A - Improvements in and relating to Semiconductor Structures - Google Patents

Abstract

1,162,565. Semi-conductor devices. IBM UNITED KINGDOM Ltd. 7 April, 1967, No. 15974/67. Heading H1K. A semi-conductor structure comprises a wafer having an isolating barrier electrically separating the opposite major surfaces and semiconductor devices formed in both major surfaces of the wafer. The isolating barrier may be a pair of PN junctions or one or more layers of insulating material. The structure may comprise an integrated circuit, or may comprise a plurality of individual devices which are separated into dice, each having a device on both faces to increase the yield of satisfactory units. In a first embodiment, N-type silicon epitaxial layers are grown on both faces of a P-type silicon substrate and P-type isolating regions are diffused through the epitaxial layers to divide them into regions in each of which a transistor, diode, resistor or other component may be produced. The transistors may be provided with highly conductive sub-collector regions by diffusing N+ type regions into the substrate before the epitaxial deposition. In a second embodiment, insulating layers of silicon carbide (SiC) are epitaxially grown on both faces of a semi-conductor wafer, layers of semi-conductor material are epitaxially grown on the SiC layers, channels are etched through the grown semi-conductor layers and are lined with insulating material, e.g. epitaxially grown SiC, or completely filled with dielectric material. Transistors and/or other devices are then formed in the isolated islands. In a first modification, the central isolation is provided by PN junctions and the lateral isolation is provided by channels filled with insulation material. In a second modification a layer of SiC and a semi-conductor layer are epitaxially deposited on only one face of a substrate, the devices being formed in the substrate and in the epitaxial semi-conductor layer. If a plurality of individual opposed pairs of devices are to be produced by dicing the wafer the lateral isolation is omitted. The structures can be contacted by mounting one face on a printed circuit and applying flying leads to the opposite face. A metallization pattern may be deposited simultaneously on both faces of the wafer.