GB1081509A - Transistor - Google Patents

Abstract

1,081,509. Semi-conductor devices. ITT INDUSTRIES Inc. April 7, 1966 [April 7, 1965], No. 15560/66. Heading H1K. As shown, Fig. 1, a planar transistor comprises a square die 1 with a square base region 2 and an emitter region (enclosed by line 5) which includes two series of fingers extending at right-angles, the fingers of each series being of successively decreasing lengths. A plurality of such transistors are produced in a wafer of N-type silicon comprising a high resistivity epitaxial layer formed on a low resistivity substrate, by diffusing in boron and phosphorus, using silicon dioxide masks, to form the base and emitter regions. Emitter and base electrodes 3, 4 are formed by exposing the base and emitter regions, evaporating a layer of aluminium on to the surface, masking and etching and then alloying the electrodes to the silicon. The wafer is then diced and emitter and base leads are connected to areas 3a, 4a by compression bonding balls formed on the ends of the leads. During production strip like regions may be diffused into the wafer between the devices, Fig. 2 (not shown), to allow measurements to be made, and to aid mask alignment. Reference has been directed by the Comptroller to Specification 993,388.