GB1070856A - Improvements in or relating to pulse circuit arrangements including bistable stages - Google Patents

Abstract

1,070,856. Associative stores. SIEMENS & HALSKE A.G. Aug. 27, 1964 [Aug. 27, 1963], No. 35081/64. Heading G4C. [Also in Division H3] A circuit arrangement is adapted to produce output pulses successively on selectably marked leads in response to input clock pulses. The arrangement is applicable to reading-out associative memories. First embodiment, Fig. 1. Each (except the first) of a series of bi-stable triggers K 0 -K 3 has an associated switch comprising a transistor TS1-TS3, the transistors normally being conductive but being turned-off in those stages which it is desired to mark. In operation, assuming stages 2 and 3 are thus marked, the triggers K 1 -K 3 are initially set to " 0 " and the trigger K 0 to "1," the output potential from side A of trigger K 0 passing via conducting transistor TS1 to energize a gate G2 which is primed by the marking potential applied to stage 2, thereby setting up trigger K 2 which is then Switched to " 1 " by the first clock pulse, this pulse resetting trigger K 0 to " 0." The output from trigger K 2 now sets up the trigger K 3 of the next marked stage. The second clock pulse resets trigger K 2 to " 0 " and switches trigger K 3 to " 1." Second embodiment, Fig. 2 (not shown). Each stage comprises a bi-stable magnetic core (K 0 -K 3 ), and associated transistors (Ts0-Ts3) connected by control windings (W 3 ) and feedback windings (W 4 ) to the associated cores. Switch transistors (Ts11- Ts13) are normally conducting but are switched off in stages where an output pulse is required. In operation, assuming stages 2 and 3 only are marked, an initial reset pulse on a lead (R) sets cores (K 1 -K 3 ) to " 0 " and the first core (K 0 ) to " 1." The first clock pulse on lead (T) switches the first core (K 0 ) to " 0," the associated transistor (Ts0) conducting during the switching period to produce a pulse which passes via a conducting transistor (Ts11) in the unmarked stage 1 to switch core (K 2 ) in the marked stage 2 by means of a winding (W 5 ). The next clock pulse resets this core (K 2 ) to " 0 " thereby producing a pulse in an output winding (not shown), and setting to " 1 " the next core (K 3 ) of the marked stage 3.