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FR3106681B1 - Architecture neuromorphique - Google Patents

Architecture neuromorphique Download PDF

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Publication number
FR3106681B1
FR3106681B1 FR2000698A FR2000698A FR3106681B1 FR 3106681 B1 FR3106681 B1 FR 3106681B1 FR 2000698 A FR2000698 A FR 2000698A FR 2000698 A FR2000698 A FR 2000698A FR 3106681 B1 FR3106681 B1 FR 3106681B1
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FR
France
Prior art keywords
track
routing circuit
input
routing
coupled
Prior art date
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Active
Application number
FR2000698A
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English (en)
Other versions
FR3106681A1 (fr
Inventor
Thomas Dalgaty
Giacomo Indiveri
Melika Payvand
Elisa Vianello
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zurich Universitaet Institut fuer Medizinische Virologie
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Zurich Universitaet Institut fuer Medizinische Virologie
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zurich Universitaet Institut fuer Medizinische Virologie, Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Zurich Universitaet Institut fuer Medizinische Virologie
Priority to FR2000698A priority Critical patent/FR3106681B1/fr
Priority to EP21152919.3A priority patent/EP3855366A1/fr
Priority to US17/248,373 priority patent/US12175358B2/en
Publication of FR3106681A1 publication Critical patent/FR3106681A1/fr
Application granted granted Critical
Publication of FR3106681B1 publication Critical patent/FR3106681B1/fr
Active legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Architecture neuromorphique La présente description concerne un circuit de routage pour router des signaux entre des circuits de neurones d’un réseau neuronal artificiel, le circuit de routage comprenant : une première cellule mémoire (302) ayant une entrée couplée à une première piste d’entrée (304) du circuit de routage et une sortie couplée à une première piste de colonne (308) ; une deuxième cellule mémoire (302) ayant une entrée couplée à une deuxième piste d’entrée (304) du circuit de routage et une sortie couplée à la première piste de colonne (308) ; et un premier circuit comparateur (310) agencé pour comparer un signal (IREAD1) présent sur la première piste de colonne (308) à un niveau de référence, et pour activer sélectivement un signal (VOUT1) sur une première piste de sortie (312) du circuit de routage en fonction de la comparaison. Figure pour l'abrégé : Fig. 3
FR2000698A 2020-01-24 2020-01-24 Architecture neuromorphique Active FR3106681B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2000698A FR3106681B1 (fr) 2020-01-24 2020-01-24 Architecture neuromorphique
EP21152919.3A EP3855366A1 (fr) 2020-01-24 2021-01-22 Architecture neuromorphique
US17/248,373 US12175358B2 (en) 2020-01-24 2021-01-22 Neuromorphic architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2000698 2020-01-24
FR2000698A FR3106681B1 (fr) 2020-01-24 2020-01-24 Architecture neuromorphique

Publications (2)

Publication Number Publication Date
FR3106681A1 FR3106681A1 (fr) 2021-07-30
FR3106681B1 true FR3106681B1 (fr) 2022-05-06

Family

ID=70978056

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2000698A Active FR3106681B1 (fr) 2020-01-24 2020-01-24 Architecture neuromorphique

Country Status (3)

Country Link
US (1) US12175358B2 (fr)
EP (1) EP3855366A1 (fr)
FR (1) FR3106681B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12437189B2 (en) * 2021-08-26 2025-10-07 Electronics And Telecommunications Research Institute Encoder and operation method thereof
EP4174724B1 (fr) 2021-10-26 2023-10-11 Commissariat à l'Energie Atomique et aux Energies Alternatives Circuit de synapses d'inférence variationnelle
FR3140974B1 (fr) * 2022-10-14 2025-04-11 Commissariat Energie Atomique Circuit neuromorphique
US20240404598A1 (en) * 2023-06-05 2024-12-05 NEO Semiconductor, Inc. 3d cell and array structures
WO2024254219A2 (fr) * 2023-06-05 2024-12-12 NEO Semiconductor, Inc. Cellules 3d et structures de réseau

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8311965B2 (en) * 2009-11-18 2012-11-13 International Business Machines Corporation Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material
US11501143B2 (en) 2013-10-11 2022-11-15 Hrl Laboratories, Llc Scalable integrated circuit with synaptic electronics and CMOS integrated memristors
US10169701B2 (en) * 2015-05-26 2019-01-01 International Business Machines Corporation Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
JP6602279B2 (ja) * 2016-09-20 2019-11-06 株式会社東芝 メムキャパシタ、ニューロ素子およびニューラルネットワーク装置
US10824937B2 (en) * 2016-12-20 2020-11-03 Intel Corporation Scalable neuromorphic core with shared synaptic memory and variable precision synaptic memory

Also Published As

Publication number Publication date
EP3855366A1 (fr) 2021-07-28
US12175358B2 (en) 2024-12-24
FR3106681A1 (fr) 2021-07-30
US20210232905A1 (en) 2021-07-29

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