[go: up one dir, main page]

FR3030881A1 - Procede de realisation d'un circuit integre en trois dimensions - Google Patents

Procede de realisation d'un circuit integre en trois dimensions Download PDF

Info

Publication number
FR3030881A1
FR3030881A1 FR1463111A FR1463111A FR3030881A1 FR 3030881 A1 FR3030881 A1 FR 3030881A1 FR 1463111 A FR1463111 A FR 1463111A FR 1463111 A FR1463111 A FR 1463111A FR 3030881 A1 FR3030881 A1 FR 3030881A1
Authority
FR
France
Prior art keywords
opening
insulating layer
dielectric material
spacer
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR1463111A
Other languages
English (en)
French (fr)
Inventor
Fabien Deprat
Perrine Batude
Yves Morand
Heimanu Niebojewski
Nicolas Posseme
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1463111A priority Critical patent/FR3030881A1/fr
Priority to EP15201708.3A priority patent/EP3038149A1/de
Priority to US14/976,958 priority patent/US20160181155A1/en
Publication of FR3030881A1 publication Critical patent/FR3030881A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H10W20/076—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H10W20/069—
    • H10W20/072—
    • H10W20/46—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
FR1463111A 2014-12-22 2014-12-22 Procede de realisation d'un circuit integre en trois dimensions Withdrawn FR3030881A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1463111A FR3030881A1 (fr) 2014-12-22 2014-12-22 Procede de realisation d'un circuit integre en trois dimensions
EP15201708.3A EP3038149A1 (de) 2014-12-22 2015-12-21 Verfahren zur herstellung eines dreidimensionalen integrierten schaltkreises
US14/976,958 US20160181155A1 (en) 2014-12-22 2015-12-21 Method for making an integrated circuit in three dimensions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1463111A FR3030881A1 (fr) 2014-12-22 2014-12-22 Procede de realisation d'un circuit integre en trois dimensions

Publications (1)

Publication Number Publication Date
FR3030881A1 true FR3030881A1 (fr) 2016-06-24

Family

ID=52589670

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1463111A Withdrawn FR3030881A1 (fr) 2014-12-22 2014-12-22 Procede de realisation d'un circuit integre en trois dimensions

Country Status (3)

Country Link
US (1) US20160181155A1 (de)
EP (1) EP3038149A1 (de)
FR (1) FR3030881A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4661066A1 (de) 2024-06-05 2025-12-10 Commissariat à l'Energie Atomique et aux Energies Alternatives Durchkontaktierungsstruktur durch metallebenen

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199409B2 (en) 2016-09-26 2019-02-05 Stmicroelectronics (Crolles 2) Sas Trench between stacked semiconductor substrates making contact with source-drain region
US9941200B1 (en) 2016-09-26 2018-04-10 Stmicroelectronics (Crolles 2) Sas Contact trench between stacked semiconductor substrates

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037379A1 (en) * 2005-08-11 2007-02-15 Ziptronix 3D IC method and device
US20090020744A1 (en) * 2007-06-29 2009-01-22 Kabushiki Kaisha Toshiba Stacked multilayer structure and manufacturing method thereof
US20130075920A1 (en) * 2011-09-22 2013-03-28 Macronix International Co., Ltd. Multilayer Connection Structure and Making Method
US20140264709A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Connecting Dies and Methods of Forming the Same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5489554A (en) * 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers
DE4400985C1 (de) * 1994-01-14 1995-05-11 Siemens Ag Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
JP2658899B2 (ja) * 1994-09-22 1997-09-30 日本電気株式会社 半導体装置の製造方法
DE19813239C1 (de) * 1998-03-26 1999-12-23 Fraunhofer Ges Forschung Verdrahtungsverfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur und vertikale integrierte Schaltungsstruktur
KR100303366B1 (ko) * 1999-06-29 2001-11-01 박종섭 반도체 소자의 배선 형성방법
US6159845A (en) * 1999-09-11 2000-12-12 United Microelectronics Corp. Method for manufacturing dielectric layer
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6500694B1 (en) * 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
JP2003031657A (ja) * 2001-07-18 2003-01-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
CN100508196C (zh) * 2004-11-05 2009-07-01 张国飙 三维存储器系统芯片
US9490212B2 (en) * 2009-04-23 2016-11-08 Huilong Zhu High quality electrical contacts between integrated circuit chips
US8642416B2 (en) * 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
JP5595977B2 (ja) * 2011-05-27 2014-09-24 株式会社東芝 半導体記憶装置、その製造方法及びコンタクト構造の形成方法
US8557632B1 (en) * 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9607942B2 (en) * 2013-10-18 2017-03-28 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device with patterned ground shielding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037379A1 (en) * 2005-08-11 2007-02-15 Ziptronix 3D IC method and device
US20090020744A1 (en) * 2007-06-29 2009-01-22 Kabushiki Kaisha Toshiba Stacked multilayer structure and manufacturing method thereof
US20130075920A1 (en) * 2011-09-22 2013-03-28 Macronix International Co., Ltd. Multilayer Connection Structure and Making Method
US20140264709A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for Connecting Dies and Methods of Forming the Same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4661066A1 (de) 2024-06-05 2025-12-10 Commissariat à l'Energie Atomique et aux Energies Alternatives Durchkontaktierungsstruktur durch metallebenen
FR3163206A1 (fr) 2024-06-05 2025-12-12 Commissariat A L' Energie Atomique Et Aux Energies Alternatives Structure d’interconnexion a vias traversant des niveaux metalliques

Also Published As

Publication number Publication date
EP3038149A1 (de) 2016-06-29
US20160181155A1 (en) 2016-06-23

Similar Documents

Publication Publication Date Title
FR3086456A1 (fr) Procede de realisation de transistors superposes
EP1292974B1 (de) Verfahren zur herstellung einer elektronischen komponente mit selbstjustierten source, drain und gate in damaszen-technologie
EP2323160A1 (de) Verfahren zur Herstellung von Feldeffekttransistoren mit einer Gegenelektrode und Halbleitervorrichtung
EP3701567B1 (de) Verfahren zur herstellung eines elektronischen bauteils mit doppelquantenpunkten
FR3060841A1 (fr) Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes
FR2757312A1 (fr) Transistor mis a grille metallique auto-alignee et son procede de fabrication
FR3043837A1 (fr) Procede de realisation de transistor a nanofil semi-conducteur et comprenant une grille et des espaceurs auto-alignes
FR2860920A1 (fr) Procede de realisation de connexions conductrices de circuits integres, et circuit integre mettant en oeuvre des telles connexions
FR2886761A1 (fr) Transistor a canal a base de germanium enrobe par une electrode de grille et procede de fabrication d'un tel transistor
FR2990295A1 (fr) Procede de formation de contacts de grille, de source et de drain sur un transistor mos
FR2664098A1 (fr) Condensateur empile d'une cellule dram et son procede de fabrication.
EP0825641B1 (de) Verfahren zur Herstellung eines Transistors mit selbstausrichtenden Kontakten
FR2884052A1 (fr) Transistor imos
EP3038149A1 (de) Verfahren zur herstellung eines dreidimensionalen integrierten schaltkreises
EP1589572B1 (de) Verfahren zur Herstellung einer integrierten Schaltung mit einem Isolationsgraben
FR2931294A1 (fr) Procede de realisation d'un transistor a source et drain metalliques
FR3007198A1 (fr) Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication
EP3104402B1 (de) Herstellung von selbstausgerichteten verbindungselementen für integrierten 3d-schaltkreis
EP3079178B1 (de) Herstellungsverfahren eines integrierten schaltkreises, in den ein fet-transistor und ein oxram-speicherpunkt integriert sind
FR2718287A1 (fr) Procédé de fabrication d'un transistor à effet de champ à grille isolée, en particulier de longueur de canal réduite, et transistor correspondant.
FR2894069A1 (fr) Fabrication de transistors mos
FR2976401A1 (fr) Composant electronique comportant un ensemble de transistors mosfet et procede de fabrication
FR2947384A1 (fr) Procede de realisation d'un transistor a source et drain metalliques
FR3063834A1 (fr) Procede de fabrication d'un dispositif semi-conducteur tridimensionnel
EP3667734B1 (de) Herstellungsverfahren von mikroelektronischen komponenten

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20160624

ST Notification of lapse

Effective date: 20170831