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FR2864318B1 - Dispositif d'organisation des donnees dans la memoire de trame d'un processeur graphique - Google Patents

Dispositif d'organisation des donnees dans la memoire de trame d'un processeur graphique

Info

Publication number
FR2864318B1
FR2864318B1 FR0315203A FR0315203A FR2864318B1 FR 2864318 B1 FR2864318 B1 FR 2864318B1 FR 0315203 A FR0315203 A FR 0315203A FR 0315203 A FR0315203 A FR 0315203A FR 2864318 B1 FR2864318 B1 FR 2864318B1
Authority
FR
France
Prior art keywords
frame memory
graphic processor
organizing data
organizing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0315203A
Other languages
English (en)
Other versions
FR2864318A1 (fr
Inventor
Alexis Vartanian
Claude Limousin
Christophe Calmejane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR0315203A priority Critical patent/FR2864318B1/fr
Publication of FR2864318A1 publication Critical patent/FR2864318A1/fr
Application granted granted Critical
Publication of FR2864318B1 publication Critical patent/FR2864318B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/10—Geometric effects
    • G06T15/40—Hidden part removal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
FR0315203A 2003-12-23 2003-12-23 Dispositif d'organisation des donnees dans la memoire de trame d'un processeur graphique Expired - Lifetime FR2864318B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR0315203A FR2864318B1 (fr) 2003-12-23 2003-12-23 Dispositif d'organisation des donnees dans la memoire de trame d'un processeur graphique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0315203A FR2864318B1 (fr) 2003-12-23 2003-12-23 Dispositif d'organisation des donnees dans la memoire de trame d'un processeur graphique

Publications (2)

Publication Number Publication Date
FR2864318A1 FR2864318A1 (fr) 2005-06-24
FR2864318B1 true FR2864318B1 (fr) 2007-03-16

Family

ID=34630476

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0315203A Expired - Lifetime FR2864318B1 (fr) 2003-12-23 2003-12-23 Dispositif d'organisation des donnees dans la memoire de trame d'un processeur graphique

Country Status (1)

Country Link
FR (1) FR2864318B1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2976945B2 (ja) * 1997-09-11 1999-11-10 日本電気株式会社 画像描画装置
JP3466173B2 (ja) * 2000-07-24 2003-11-10 株式会社ソニー・コンピュータエンタテインメント 画像処理システム、デバイス、方法及びコンピュータプログラム
FR2840705A1 (fr) * 2002-06-06 2003-12-12 Artabel Procede et dispositif d'equilibrage de charge au sein d'un ensemble (cluster) d'ordinateurs utilises en parallele pour des applications graphiques

Also Published As

Publication number Publication date
FR2864318A1 (fr) 2005-06-24

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