FR2861234A1 - ENCRYPTION OF DATA IN AN ELECTRONIC APPARATUS WITH MULTIPLE SYMMETRIC PROCESSORS - Google Patents

Abstract

For the encryption of data to be stored in a memory (23) external to a circuit, provision is made to store in the external memory encrypted data words (Ci) in association with an initialization vector (IVi) and a key identifier (KIDi) associated with a secret key (Ki) used to encrypt it.

Description

DATA ENCRYPTION IN AN ELECTRONIC APPARATUS A

MULTIPLE SYMMETRIC PROCESSORS

  The present invention generally relates to the encryption or encryption of data for use in one or more processors, when these data are to be stored in a memory external to the processors.

  It finds applications, in particular, in electronic devices having a symmetric processor architecture and shared external memory (or SMP architecture, the "Symetric Multi-Processor"). More specifically, the present invention relates to applications in which it is desired to prevent an unauthorized user from accessing data in a usable manner, and wherein said data must, at least in part, be accessed by more than one circuit.

  Reference is here made to the term "data" to designate any binary code regardless of whether they are executable programs, or binary data that are processed by these programs. In addition, reference is made to the term "circuit" to denote any functional unit of an electronic device connected to other functional units via one or more communication buses, whether it be a processor , a device controller (for example a disk controller), a network card, etc.

  Figure 1 schematically illustrates the SMP architecture of an electronic apparatus to which the present invention applies. Several processors 2 (CPU) are coupled to an external memory 4 (EXT MEM), via one or more buses 3. It is possible to define a zone 1, called a secure zone, inside which there is a or multiple processors 2, and within which it is considered that the processed data is not likely to be pirated. In practice, the secure area 1 usually includes one or more integrated circuit chips corresponding to respective processors, the memory 4 being another chip that does not belong to the secure area. In addition, other circuits 5, such as a disk controller (DSK CTRL) or a network card (NET LARD), can be connected to the processors 2 via the buses 3.

  The encryption to which the present invention applies relates more particularly to that of the data transiting on the bus or buses 3, between the memory 4 and the processor or processors 2 of the zone 1. In the jargon of the person skilled in the art, reference is made to encryption of the memory or encryption of the bus. This encryption consists of coding the data stored in the memory 4 by means of a bus encryption key known by the processors concerned.

  Examples of solutions for encrypting a memory external to a microprocessor are described in U.S. Patents 5,825,878, 5,982,887, and 6,041,449.

  These solutions are not suitable for SMP architecture systems, since the same bus encryption key must be used to encrypt and decrypt the data while each processor uses a bus encryption key which is clean. Indeed, measures must be taken to allow another processor of the secure area to decrypt, for use, encrypted data and stored in the external memory shared by another processor of said secure area. These measurements must, however, be compatible with the secret key character of the bus encryption keys.

  Another constraint is related to the encryption method used. In the prior art, block ciphers are generally used with algorithms of the DES ("Data Encryption System") or AES ("Advanced Encryption System") type, according to a mode of electronic coding book called ECB mode ("Electronic Code Book ") or a mode by block chaining said mode CBC (" Cipher-Block Chaining "). The size of a block depends on the encryption algorithm used. In ECB mode, two identical blocks are encrypted in the same way. Attacks are therefore possible, by the so-called "dictionary" technique, insofar as the redundancy of identically encrypted messages can allow the identification of messages in the clear. In contrast, in CBC mode, each block is encrypted based on the previous blocks. This mode is more robust. Nevertheless, it requires sequential access to the memory, which makes it incompatible with the data encryption which one wishes to be able to access randomly in the external memory.

  The present invention aims at proposing, in the context of an SMP-based electronic apparatus, a new technique of encryption, by a processor, of data to be stored in a memory external to this processor, when the data must be able to be exploited more of a processor.

  For this purpose, a first aspect of the invention provides a method of encryption in a circuit of an electronic device, of data to be stored in a memory external to said circuit, comprising the steps of: - selecting a secret key, from a list of secret keys respectively stored in a set of registers of the circuit each associated with a key identifier, at least one of said keys being a key shared with at least one other circuit of the electronic apparatus; - Cut the data into a stream of data words of determined size; and, continuously for each data word, generating a pseudo-random number of determined size by means of a pseudo-random generator implementing a generation algorithm according to said secret key and a value-changing initialization vector each data word; - combine the data word and the corresponding pseudo-random number, to generate an encrypted data word; then, storing in said external memory each encrypted data word 25 in association with the initialization vector and the key identifier associated with the secret key used to encrypt it.

  A second aspect of the invention provides a method of decrypting, in a circuit of an electronic apparatus, data stored in the form of ciphered data words in a memory external to said circuit, comprising the steps of: - reading in said external memory an encrypted data word and an initialization vector and a secret key identifier respectively associated with said data word; selecting a secret key, from a list of secret keys respectively stored in a set of registers of the circuit and at least one of which is a key shared with at least one other circuit of the electronic device, and from in addition to said identifier; and, continuously for each encrypted data word, generating a pseudo-random number of determined size by means of a pseudo-random generator implementing a generation algorithm according to said secret key and said initialization vector; and - combining the data word and the corresponding pseudorandom number, to generate a decrypted data word.

  A third aspect of the invention relates to a device for implementing an encryption method according to the first aspect, comprising: a set of registers storing respective secret keys, at least one of which is a key shared with another circuit of the electronic apparatus, each associated with a key identifier; a secret key selection unit adapted to select a secret key from the list of keys stored in said set of registers; a segmentation unit adapted to cut the data so as to form a stream of data words of a determined size; an initialization vector generator adapted to generate a stream of initialization vectors changing in value with each data word; a pseudo-random number generator implementing a generation algorithm adapted to generate, for each data word, as a function of said secret key and of a predetermined one of said initialization vectors, a pseudo-random number of determined size; a combination unit adapted to continuously combine the data word and the corresponding pseudorandom number, to generate an encrypted data word; and means for storing in said external memory each encrypted data word in association with said determined initialization vector and the key identifier associated with the secret key used to encrypt it.

  In addition, according to a fourth aspect, the invention proposes a device for implementing a decryption method according to the second aspect. This device comprises: a set of registers storing respective secret keys, at least one of which is a shared key, each associated with a key identifier; reading means for reading from said external memory a data word as well as an initialization vector and an identifier of a secret key respectively associated with said data word; selection means for selecting, for each data word, a secret key from a list of keys stored in said registers and further from said key identifier; a pseudo-random number generator implementing a generation algorithm adapted to generate, for each data word, as a function of said secret key and said initialization vector, a pseudo-random number of determined size; and, a combining unit adapted to combine the data word and the corresponding pseudo-random number, thereby decrypting said data word.

  A fifth aspect of the invention relates to a circuit comprising an encryption / decryption unit forming an encryption device according to the third aspect and a decryption device according to the fourth aspect. The set of registers, the pseudorandom number generator and the combination unit are then common to both devices.

  According to a sixth and last aspect, the invention also proposes an electronic apparatus comprising at least two circuits according to the fifth aspect, wherein at least one of the secret keys is shared between said circuits so as to form a secure subsystem.

  The keys are said to be shared in the sense that other circuits of the electronic device know them, for example the circuits belonging to the secure zone, that is to say the secure subsystem. The invention thus provides a solution that makes it possible to individualize the encryption according to the processor that carries it out, while ensuring that all the processors having the authorization to use the data stored in the external memory will be able to decrypt them.

  The encryption according to the invention is of the type of a streaming encryption ("Stream Cipher"), which is simpler and therefore faster than block ciphering. Continuous encryption is also insensitive to dictionary attacks because the same data word is encrypted in a different word for each encryption.

  In addition, the encryption according to the invention is compatible with random access to the external memory.

  Other features and advantages of the invention will become apparent on reading the description which follows. This is purely illustrative and should be read in conjunction with the accompanying drawings in which: - Figure 1 is a diagram of an electronic device to which the various aspects of the invention can be applied - Figure 2 is a block diagram an example of a circuit coupled to an external memory, according to an embodiment of a circuit according to the invention.

  In the drawings, the same elements are designated by the same references in the different figures. For the sake of clarity, only the steps of the method and the elements that are necessary for the understanding of the invention have been shown and are described hereinafter. In particular, not all elements of a circuit have been detailed, the invention using components known for its implementation.

  A feature of the present invention is to encrypt data (programs, arbitrary bit data) to be stored in an external memory shared by several circuits of an electronic device. The data is encrypted by means of a secret key, specific to the circuit performing the encryption, which may be different from the secret key used by other circuits for comparable encryption.

  In order to allow the use of data encrypted by more than one circuit, at least some of the secret keys that can be used by a circuit are shared with one or more other circuits, that is to say they are known from these circuits while being secretive vis-à-vis the rest of the system.

  A shared key defines a circuit subsystem that can use common data stored in external memory. Typically, this subsystem may correspond to a secure zone as presented in the introduction with reference to the diagram of FIG.

  In addition, the data is stored in the external memory in association with an identifier of the secret key used to encrypt them. This identifier allows authorized circuits to determine the secret key to be used for decryption of data. This identifier may correspond to an index in a set of internal registers in which the secret keys supported by a circuit are respectively stored. It is therefore not the secret key itself which is stored with the data encrypted by it, but the identifier of this secret key. The disclosure of the identifier by storage in the external memory provides no weakness of encryption, since only authorized circuits can know the secret key to use from this identifier.

  Another feature of the present invention is to provide encryption and decryption continuously, during transfers between a circuit and the external memory. This continuous encryption is obtained from a division of the data into words of determined size which are then stored in encrypted form in the external memory. Encryption is also expected to use the combination of a data word with a pseudo-random number, which is generated from the secret key and an initialization vector.

  Advantageously, the initialization vector changes value for each word, preferably in a random manner, in order to reinforce the security of the encryption. The initialization vector used for the encryption of a data word is advantageously stored in the external memory in association with the encrypted data word, as well as the identifier of the secret key as indicated above. This eliminates problems related to continuous encryption that are classically incompatible with direct random access to a memory.

  The diagram of FIG. 2 shows the essential means of an exemplary embodiment of a circuit suitable for implementing the encryption method (illustrated by the arrows in solid lines) and for the implementation of the decryption method ( illustrated by the arrows in dotted lines).

  The circuit here is a processor 2 (CPU) comprising a processor core 44 (CORE), cache memories 33 and 34 (CACHE), an encryption key selection unit (KSEL) 31 (KSEL), and a unit 38 (BEU) encryption / decryption.

  The unit 38 comprises a data segmentation unit 22 (SEGM), a set 32 (KREG) of secret key registers, a first pseudo random generator 24 (IVGEN), a cache memory 25 (IVCACHE), a key register 12 and an initialization vector register 13, a second pseudo random generator 10 (PRNG), and finally a combination unit 11.

  The segmentation unit 22 has the function of segmenting the data to be encrypted (DATA) that it receives from the processor core 44, into data words (W) of determined size. A data word can thus comprise a single bit. Preferably, however, the size of a word is one byte, i.e. one word comprises eight bits.

  Each register of the set 32 is adapted to non-volatile store a secret key (K) to which is associated a secret key identifier (KID). All or part of the secret keys can be provided to the processor via a secure channel, for example during the manufacture of the system. At least some of the secret keys may, conversely, be generated internally according to an ad-hoc algorithm whose description would be beyond the scope of this presentation. In a preferred example for its simplicity, the identifier is an index, such as a register number, making it possible to access the corresponding secret key from the list of secret keys supported by the processor and stored in the set 32.

  The random generator 24 is adapted to generate initialization vectors, at the rate of a data word initialization vector to be encrypted, according to any pseudo-random algorithm.

  The cache memory 25 is adapted to store pairs each formed of an initialization vector and a key identifier associated with a data word.

  The register 12 is adapted to store an encryption key, namely one of the secret keys stored in the set of registers 32. This register is indicated here for the sake of clarity, but it can be omitted if the means for managing the set of adapted registers 32 are provided.

  The initialization vector register 13 has the function of storing the initialization vector generated continuously by the pseudo-random generator 24. Preferably, the size of the initialization vectors is equal to the size of the data words to be encrypted.

  The role of the pseudo-random generator 10 is to continuously generate a stream of pseudorandom numbers (PN), with such a number per data word to be encrypted. Each pseudo-random number is generated from the encryption key stored in the register 12 and the initialization vector stored in the register 13, the latter changing value to each data word.

  In one example, the combining unit is an exclusive-OR (XOR) gate. The pseudo random generator 10 and an XOR gate form a cryptosystem which, in itself, is well known to those skilled in the art. The words of encrypted data that it outputs are the same size as the data words (before encryption) received as input. Such a cryptosystem has the advantage of providing a simple encryption algorithm, so fast, and whose robustness vis-à-vis security attacks is determined by the internal details of the pseudo-random generator 10. Plus the PN number flow generated by the latter is random, better is the security of the encryption algorithm. Another advantage of an XOR gate encryption algorithm is that the decryption is done in the same way as the encryption, which simplifies the hardware design of the cryptosystem.

  The operation of the circuit in encryption mode, will now be explained, considering the arrows in solid lines shown in Figure 2.

  The encryption mode is typically activated by the processor core 44 when DATA data stored in or passing through the cache memory 34 must be written to the external memory 23, and must for this purpose pass through the communication bus 3.

  The heart 44 controls the selection unit 31 to select one of the secret keys stored in the register set 32. In one example, the unit 31 selects a secret key identifier KIDi associated with a certain secret key . This identifier KIDi is provided by the unit 31 to the encryption unit 38.

  In the encryption unit 38, the key Ki associated with the identifier KIDi is read in the register set 32 by means of said identifier KIDi, used for example as an index in the path of the set of registers 32. The key Ki is then stored in the register 12.

  Furthermore, the core 44 controls the cache memory 34 so that the data DATA is supplied to the encryption unit 38, and more particularly to the input of the segmentation unit 22. The latter delivers a corresponding bit stream Wi each to a segment of the DATA data stream. Meanwhile, the pseudo-random generator 24 generates a flow of initialization vectors IVi, at the rate of delivery of the data words Wi by the unit 22, these initialization vectors changing value to each of the words Wi. In other words, each data word Wi is associated with an initialization vector IVi whose value is different from that of the initialization vector associated with the previous word in the data word stream. The initialization vectors IVi, which are continuously generated, are each time stored in the register 13.

  For each data word Wi, the following operations are then performed continuously.

  On the one hand, the pseudo-random generator 10 generates a pseudo-random number PNi as a function of the secret key Ki stored in the register 12 and the initialization vector IVi stored in the register 13. Each time, the number PNi is delivered on a second input of the XOR gate 11.

  On the other hand, the data word Wi and the corresponding pseudo-random number PNi are combined by the XOR gate 11 so as to generate an encrypted data word Ci.

  The encryption unit 38 then stores the word Ci in the external memory 23, as well as and in association with the initialization vector IVi, and the secret key identifier KIDi that were used to encrypt it. For this writing, the encrypted data word Ci, the initialization vector IVi and the secret key identifier KIDi pass through the communication bus 3. However, this is not a security weakness of the encryption method since the word Ci is encrypted, where the initialization vector IVi is not sufficient in itself to perform the decryption, and where the identifier KIDi has no meaning for another circuit which does not have the secret key associated with this identifier.

  The operation of the circuit in decryption mode is now explained by considering the arrows in dashed lines shown in FIG.

  Under the control of processor core 44, encrypted data words are read into external memory 23 at specific addresses. Each word Cj thus read is delivered on the first input of the gate XOR 11. For each word Cj, the initialization vector IVj and the secret key identifier KIDj which are associated with this word, are also read in the external memory 23.

  From the identifier KIDj, the decryption unit 38 selects the secret key Kj associated with this identifier, looking in the list of secret keys stored in the set of registers 32. The key Kj thus selected is stored in the register 12. In parallel, the vector IVj is stored in the register 13.

  In fact, the vector IVj and the identifier KID] transit through the cache memory 25. This caching makes it possible to improve the performance of the decryption unit, in terms of decryption speed. The pseudo-random generator 10 then generates a pseudo-random number PNj from the key Kj stored in the register 12 and the vector IVj stored in the register 13. The number PNj is delivered on the second input of the XOR gate 11.

  The XOR gate 11 combines the encrypted data word Cj and the pseudo-random number PNj and outputs a data word Wj corresponding to the deciphered word Cj.

  The decrypted data word Wj is then supplied to the processor core 44 through the cache memory 33.

  Of course, the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. In particular, the invention can be implemented with any known continuous encryption algorithm, conditioning the pseudo-random generator 10 from the secret key and the initialization vectors. In addition, it is assumed that the practical embodiment of the invention is within the abilities of those skilled in the art from the functional indications given above. In this respect, it will be noted that, according to one embodiment of the invention described here, the various encryption and decryption tools are made by hardware resources of the processor. However, implementation by software resources is of course conceivable.

  In addition, the invention is not limited in any way to an application in a processor. On the contrary, an encryption / decryption unit such as the unit 38 described above can be provided in other circuits of an electronic device as shown in FIG. 1, in particular in the disk controller or in the card. network.

  It should also be noted that not all the data stored in the external memory need be encrypted. In this regard, it can be provided that a key identifier having the value zero corresponds to the absence of encryption of the corresponding data word, that is to say that said data word is stored in clear in the external memory .

Claims (14)

  1. A method of encryption in a circuit (2) of an electronic device, of data to be stored in a memory (23) external to said circuit, comprising the steps of: - selecting a secret key (Ki), from a list of secret keys (K) respectively stored in a set of registers (32) of the circuit each associated with a key identifier (KID), at least one of said keys being a key shared with at least one other circuit of the electronic device; cutting the data into a stream of data words (Wi) of determined size; and, continuously for each data word, generating a pseudo-random number (PNi) of determined size by means of a pseudo-random generator implementing a generation algorithm according to said secret key and a vector of initialization (lVi) changing value at each data word; - combine the data word and the corresponding pseudo-random number, to generate an encrypted data word (Ci); then, - storing in said external memory each encrypted data word in association with the initialization vector and the key identifier (KIDi) associated with the secret key used to encrypt it.   2. Method according to claim 1, wherein the combination is of the exclusive-OR type, the size of the pseudo-random numbers being equal to the size of the data words.   3. Method according to any one of the preceding claims, wherein at least one of the secret keys is specific to the circuit.   4. A method of decrypting, in a circuit (2) of an electronic apparatus, data stored in the form of ciphered data words in a memory (23) external to said circuit, comprising the steps of: - reading in said external memory an encrypted data word (Cj) and an initialization vector (lVj) and a secret key identifier (KlDj) respectively associated with said data word; selecting a secret key (Kj), from a list of secret keys (K) respectively stored in a set of registers (32) of the circuit and at least one of which is a key shared with at least one other circuit of the electronic apparatus, and further from said identifier; and, continuously for each encrypted data word, generating a pseudo-random number (PNj) of determined size, by means of a pseudo-random generator (10) implementing a generation algorithm according to said secret key and said vector initialization; and, - combining the data word and the corresponding pseudo-random number, to generate a decrypted data word (Wj).   5. The method of claim 4, wherein the combination is of the exclusive-OR type, the size of the pseudo random numbers being equal to the size of the data words.   The method according to any one of claims 4 and 5, wherein the initialization vector and the secret key identifier read in the external memory are stored in association with each other in a cache memory ( 25) of the circuit.   7. Device for implementing an encryption method according to any one of claims 1 to 3, comprising: - a set of registers (32) storing respective secret keys (K), at least one of which is a key shared with another circuit of the electronic device, each associated with a key identifier (KID); a secret key selection unit adapted to select a secret key (Ki) from the list of keys stored in said set of registers; - a segmentation unit (22) adapted to cut the data so as to form a flow of data words (Wi) of determined size; an initialization vector generator (24) adapted to generate a flow of initialization vectors (lVi) changing value to each data word; a pseudo-random number generator (10) implementing a generation algorithm adapted to generate, for each data word, as a function of said secret key and of a predetermined one of said initialization vectors, a pseudo-random number (PNi ) of a determined size; a combination unit (11) adapted to continuously combine the data word and the corresponding pseudorandom number, to generate an encrypted data word (Ci); and means for storing in said external memory each encrypted data word in association with said determined initialization vector and the key identifier associated with the secret key used to encrypt it.   8. Device for implementing a decryption method according to any one of claims 4 to 6, comprising: a set of registers storing respective secret keys, at least one of which is a shared key, in association each with a key identifier; reading means for reading from said external memory a data word as well as an initialization vector and an identifier of a secret key respectively associated with said data word; selection means for selecting, for each data word, a secret key from a list of keys stored in said registers and further from said key identifier; a pseudo-random number generator (10) implementing a generation algorithm adapted to generate, for each data word, as a function of said secret key and said initialization vector, a pseudo-random number of determined size; and a combination unit adapted to combine the data word and the corresponding pseudo-random number so as to decode said data word.   9. A circuit comprising an encryption / decryption unit (38) forming an encryption device according to claim 7 and a decryption device according to claim 8, the set of registers, the pseudo random number generator and the combination unit being common. to both devices.   The circuit of claim 9, wherein the combining unit is an exclusive-OR gate, the size of the pseudo-random numbers being equal to the size of the data words.   11. Circuit according to any one of claims 9 and 10, wherein at least one of the secret key is specific to the circuit.   Circuit according to any one of claims 9 to 11, wherein at least one of the secret keys is shared with another circuit of an electronic device.   The circuit of any one of claims 9 to 12, wherein the encryption / decryption unit comprises a cache memory (25) in which the initialization vector and the secret key identifier read in the external memory are stored in association with each other.   An electronic apparatus comprising at least two circuits according to any one of claims 9 to 13, wherein at least one of the secret keys is shared between said circuits so as to form a secure subsystem.