FR2728102A1 - METHOD FOR MANUFACTURING INTEGRATED CIRCUIT MOS TRANSISTORS - Google Patents

Abstract

The present invention relates to a method for manufacturing MOS transistors on a semiconductor wafer comprising the steps of forming field oxide regions (16) delimiting active regions (12); depositing a gate oxide (20) on the active regions; depositing a first layer of conductive material (22) at least on the active regions and the adjacent parts of the field oxide regions; planarize the resulting upper surface; depositing at least a second layer of conductive material (24) on at least part of the first planarized layer of conductive material; and etching selected patterns on the first and second layers of conductive material.

Description

 The present invention relates to the manufacture of integrated circuits on semiconductor wafers and more particularly to the manufacture of MOS transistors with a gate length of less than 0.6 μm.

 In the context of the manufacture of semiconductor integrated circuits, we are constantly seeking to manufacture increasingly smaller devices. This means that the circuits are more efficient in terms of operating speed and contamination and occupy less space on a semiconductor substrate.

 The dimensions of the MDS transistors depend to a large extent on the minimum possible length of the gate electrode. This length should be carefully controlled, as it largely determines the characteristics of the completed MOS device. MOS devices typically have gate lengths of 0.5 µm, with values on the order of 0.35 µm being expected for the near future.

 FIGS. 1 and 2 illustrate a conventional method for forming the gate electrode of MOS transistors in an integrated circuit. 2 shows a sectional view along line AA of Figure 1.

 In the step illustrated in FIGS. 1A and 2A, a semiconductor substrate 10 has an upper surface which is divided into active regions 12 and field regions 14. The field regions are coated with a field oxide 16 on their upper surface. This field oxide typically has a thickness of about 500 rm, and about half of its thickness is below the level of the upper surface of the semiconductor in the active area. At the interfaces 18 between the field regions 14 and the active regions 12, the field oxide gradually thins.

A layer of gate insulator is pierced above the field oxide 16 in the field region 14 and above the semiconductor 10 in the active region 12. This layer of gate insulator may be formed silicon oxide, about 10 nm thick. A first conductive layer 22 rests on the gate oxide and covers the entire upper face. This conductive layer can typically consist of polycrystalline silicon or amorphous silicon.

 In the step illustrated in FIGS. 1B and 2B, a layer of positive photosensitive product (hereinafter called resin) 24 is applied over the entire upper surface. A mask 26 having transparent regions 28 and opaque regions 30 is placed above the upper face of the wafer. Light 32 of wavelength suitable for modifying the resin is then applied to the mask and passes through transparent regions of the latter. An appropriate etching agent is then used to remove the modified zones from the resin (this in the case of a positive resin - in the case of a negative resin it is the unmodified zones which will be eliminated and the opaque and transparent regions mask are interchanged).

 At the stage illustrated in FIGS. 1C and 2 C, the result of this engraving has been shown. Part 34 of the resin layer remains above regions which must become the gates of the MOS transistors and the interconnection lines.

 Appropriate etching is then used to remove the first uncovered conductive layer of the remaining resin 34, and then to remove the remaining resin 34 itself.

 Figures 1D and 2D show the shape of the wafer at this stage. A part 36 of the first conductive layer remains in the same pattern as that defined by the remaining layer of resin 34. This region 36 represents the gate electrodes of the Moe transistors and the lines of irreconnection.

FIGS. 1E and 2E represent the surface of the wafer after a subsequent treatment by which the transistors
MOS are trained. Lightly doped source and drain regions 38 are formed in the semiconductor surface with a conductivity type opposite to that of the semiconductor substrate.

Spacers 40 are then formed by an appropriate method, for example by deposition of silicon oxide and etching. The gate oxide layer is removed from the areas other than those located under the gate electrode 36 and the spacers 40. Source and drain waxed doped regions 42 are then formed in the parts of the active region 12 not covered. of the gate electrode 36 or of the spacers 40. These source and drain regions have a doping type opposite to that of the semiconductor substrate and a doping level higher than that of the lightly doped source and drain regions 38.

 As shown in FIGS. 1F and 2F, a highly conductive material such as titanium silicide 44 can be formed on the upper surfaces of the gate electrodes 36 and of the source and drain regions 42. A very conductive layer of titanium silicide can be formed by spraying metallic titanium over the entire surface of the wafer. A heat treatment is then applied and the titanium on the silicon rons - either the polycrystalline silicon gate electrodes or the source / drain regions - reacts to form titanium silicide. Titanium deposited on other materials, such as silicon oxide does not react. Selective etching then removes all regions of unreacted titanium leaving in place a layer of titanium silicide on only the regions of grid, source and drain.

 A connection to the highly conductive layer can be made during subsequent steps, for example by providing an insulating layer over the entire wafer by etching contact holes towards the highly conductive mouthpiece, and by rolling these contact holes from a conductive material such as tungsten and applying a conductive layer such as tungsten or aluminum on all of the folded contacts.

 The completed gate electrode typically has a thickness of 350 nm of rrnrn as the intercoenemion lines over the field region.

 In current integrated circuit technologies, several levels of metallization are necessary. Obtaining multiple metallic layers and interposed insulating layers requires very flat surfaces at each level. In current processes, up to five levels of interconnect metal and several levels of polycrystalline silicon are used. The MOS transistor illustrated in Figures 1 and 2 does not have a very planar upper surface and causes planarization problems during the formation of a dielectric layer above the interconnection lines. The thickness of the interconnection lines can also lead to the formation of gaps during the formation of the dielectric layer above the interconnection lines.

 Referring to FIG. 1B, it can be seen that the definition of the grid during a photographic step is deteriorated by the reflection of light 32 coming from the oblique interface between the resin 24 and the first layer conductive 22 at interface 18. This can lead to the final gate electrode 36 being shorter than desired, since the reflected light can act to expose and therefore modify the edges of the resin located under opaque regions 30 of mask 26. This effect varies with the distance from the gate electrode to the field regions. The gate lengths produced vary from up to 0.1 µm depending on their distance from the field regions. As it has been explained before, precise control of the gate lengths of the transistors is essential to the manufacture of reliable transistors. This problem is not significant for gate lengths greater than 1 µm since a variation of 10% in gate length is tolerable. However, with gate lengths less than 0.5 pin, such variations are no longer tolerable. To resolve this problem, mask 26 commonly carries patterns 30 which are 0.1 µm longer than necessary . This means that transistors far from the field regions will have gate lengths of 0.1 µm longer than necessary and will therefore be slower to operate, especially for low supply voltages such as 3.3 V. We can therefore no longer reduce the dimensions of a circuit.

 A variation in transistor gate length leads to variations in transistor parameters which must be carefully controlled to ensure proper operation of the integrated circuit. The following parameters are particularly affected by variations in gate lengths: the conduction saturation current, the leakage current in the blocked state and the breakdown or piercing voltage of the channel.

 The fact that there is a difference in height between the active regions and the field regions during the photographic step can cause certain defoealization effects as regards the definition of the characteristics in one of the regions due to a depth limited field of the photographic stage.

 Figure 2E illustrates another problem that arises with the process described above. During the formation of the spacers 40, parasitic spacers 46 may be formed on the first conductive layer 36 where it passes over the interface 18 between an active region 12 and a field region 14, due to the presence of a step in the first conductive layer, caused by the difference in height of the two regions.

 FIG. 2F shows that these parasitic spacers 46 then prevent the formation of a very conductive layer, such as titanium silicide, over the locators of the gate electrode 36 which are covered by the parasitic spacers, so that titanium silicide cannot form above the oryde. There is therefore a solution of continuity of the highly conductive layer, which means that, at these locations, the conduction takes place only through the first conductive layer. When the conductive layer is made of polycrystalline silicon, this introduces an undesirable notable series resistance in the interconnection lines.

 This is amplified by the fact that the light reflections coming from the interface of the first conductive layer and of the resin described above also give rise to an overexposure of the resin in the vicinity of the interface 18 between the active region 12 and the edge region 14. In addition, the difference in height of the two regions causes the resin layer 24 to be thinner in this region. These reasons cause the first conductive layer under the parasitic spacers 46 to be thinner than desired, which further increases the series resistance introduced by the breaks in continuity of the highly conductive layer.

 Thus, an object of the present invention is to provide a method for obtaining MS transistors of very short determined gate length.

 Another object of the present invention is to provide a method making it possible to avoid the formation of parasitic spacers during the manufacture of MOS transistors.

 Another object of the present invention is to improve the flatness of MDS transistors.

 Another object of the present invention is to improve the reliability of the metallizations placed on FDS transistors of an integrated circuit.

 To achieve these objects, the present invention provides a method for manufacturing transistors K) S for integrated circuits on a semiconductor wafer comprising the following steps: forming chanc alcade regions on an upper surface of the wafer, adjacent to regions active; forming a gate oxide on the active regions on the surface of the wafer; depositing a first layer of conductive material at least on the active regions of the wafer and the adjacent parts of the field oxide regions; plaaariser the resulting upper surface; depositing a second layer of conductive material on at least part of the first planarized layer of conductive material; and etching selected patterns on the first and second layers of coating material.

 According to an embodiment of the present invention, the planarization step is carried out by chemical mechanical polishing.

 According to an embodiment of the present invention, the conductive material of the first layer is polycrystalline silicon and the chemical mechanical polishing is carried out using a mud of potassium hydroxide and alumina in water.

 According to an embodiment of the present invention, the field oxide has a thickness greater than 300 rm and the gate aacyde a thickness less than 12 nm.

 The present invention also provides a transistor S formed in an integrated circuit having a gate electrode disposed on a layer of gate oxide and between two regions of field oxide, in which the gate electrode comprises first and second layers. of conductive material, the second layer covering at least partially the first layer, the common surface between the first and the second layer of conductive material being coplanar with the adjacent upper surface of the neighboring field oxide region.

 According to an embodiment of the present invention, the first layer of conductive material comprises lin polycrystal silicon.

 According to an embodiment of the present invention, the second layer of conductive material comprises lin polycrystal silicon.

These objects, characteristics and advantages as well as others of the present invention are described in detail in the following description of a particular embodiment made, without implied limitation, in relation to the attached figures among which
FIGS. 1 and 2 represent stages in the formation of a transistor M) S of an integrated circuit, according to the prior art; and
Figures 3 and 4 show corresponding steps of forming an MS transistor in an integrated circuit 1 according to the invention.

 Figures 3 and 4 illustrate manufacturing steps according to the invention. Figures 4A to 4F are respective sectional views along line AA of Figures 3A to 3F.

 Figures 3A and 4A show a semiconductor wafer such as that of Figures 1A and 2A. A semiconductor substrate 10 has an upper surface divided into active regions 12 and field regions 14. The field regions are coated with a field oxide 16. At the interfaces 18 between the active regions 12 and the field regions 14, the field oxide 16 gradually thins out. A gate oxide layer 20 is located on the field oxide 16 in the field area 14 and on the semiconductor 10 in the active area 12. A first conductive layer 22, for example made of polycrystalline silicon, rests on the grid oxide and covers the entire upper face. This first layer of conductive material has a thickness greater than the difference in height between the upper surface of the active region and the upper surface of the field region, for example a thickness of 200 nm or more.

 Camp this is shown in Figures 3B and 4B, the upper surface of the first conductive layer 22 is planarized at the upper surface of the field oxide 16 to form a coplanar surface 50. This can be achieved by several methods, by example by depositing a planarization layer such as a glass deposited with the spinner, followed by etching at an etching speed substantially equal for the material of the first conductive layer 22 and that of the planarization layer. Preferably, this planarization is carried out by a chemical mechanical polishing process which removes the polycrystalline silicon layer until a breakpoint is detected following the exposure of the oxide layer. Field 16. This breakpoint detection can be carried out by any known method, for example by considering the surface conductivity of the wafer, the mechanical resistance to the action of rotation of the polishing taxon, or an audible detection of sounds. emitted by the wafer, all these parameters changing when a significant surface of the field oxide is exposed to the polishing pad, indicating the time when the first conductive layer was removed from the field regions.

A polishing slurry suitable for the removal of polycrystalline silicon consists of alumina particles in aqueous potassium hydroxide solution. A certain amount of overpolishing is generally used to ensure complete removal of the polycrystalline silicon from the field oxide regions.

 As shown in FIGS. 3C and 4C, a second conductive layer 52, and possibly others, are applied to the entire flat surface 50 of the first conductive layer 22 and the field oxide 16. This second conductive layer can be polycrystalline silicon or any other suitable conductive material. A resin layer 24 is then applied to the entire upper surface of the second conductive layer. The mask 26 is placed on the upper surface of the wafer. Light 32 of suitable length to modify the resin is applied to the mask and passes through the transparent regions of the mask. A suitable etchant is then used to remove the modified areas from the resin.

 The thickness of the second conductive layer may be less than the thickness of the first conductive layer. If it is desired to form a layer of titanium silicide on a second conductive layer of polycrystalline silicon, this second conductive layer must be thick enough to allow effective formation of silicide. The second conductive layer may for example have a thickness of between 40 and 100 nin. In any case, the thickness of the second conductive layer will be less than the thickness of the interconnection layers of FIGS. 1 and 2.

 Figures 3D and 4D illustrate the result of this engraving. Part 34 of the resin layer remains in place, above regions which are to become grids of hDS transistors and interconnection lines.

 A suitable etching is then used to remove the first and second conductive layers 22 and 52 at the locations where they are not covered by the part 34 of remaining resin and the remaining resin 34 is then removed.

Figures 3E and 4E show the surface of the wafer at this stage. A portion 54 of the second conductive layer remains in place, exactly covering a remaining portion 36 of the first conductive layer in the same pattern defined by the opaque regions 30 of the mask 26. The remaining portions 54, 36 represent the gate electrodes of the transistors M) S and the interconnection lines. The parts of interconnection lines passing over the field oxide regions 16 take only part of the second conductive layer, while the gate electrodes of the transistor
MOS and any other line formed above the active region includes portions of the first and second conductive layers. These lines can have approximately the same thickness as the equivalent lines shown in FIGS. 1 and 2. The gate oxide layer 20 exists only above active regions and field oxide regions whose upper surface is located under the flat surface 50.

 Other steps are carried out to complete the Soft transistors. Lightly doped drain regions 38 are formed in the surface of the semiconductor, of conductivity type opposite to that of the semiconductor substrate. Spacers 40 are also formed, by a suitable method such as oxide deposition and etching. The gate oxide layer 20 is then removed from the active region elsewhere than under the gate 36, 54 or the spacers 40. Source and drain regions 42 are also formed in the parts of the active region 12 not covered with 1 gate electrode 36, 54 or spacers 40. These source and drain regions have a conductivity type opposite to that of the semiconductor substrate and a higher doping level than that of the weakly doped drain regions 38.

 Rod that is shown in Figures 3F and 4F, a layer of highly conductive material such as titanium silicide 44 can be formed on the upper surfaces of the gate electrode 36, 54 and source and drain regions 42. A connection to this highly conductive layer can be achieved by any suitable method.

 The final transistor obtained by this process, shown in Figures 3F and 4F, has a much more planar upper surface than the transistor of the prior art. This greatly facilitates the formation of a flat insulating layer on top of such transistors and the same is true for the metallic layers deposited subsequently. The existence of a flat surface before the depat of each metallic layer improves the reliability of the interconnection layers subsequently formed from these layers, since the problems, well known in the art, of aninci are eliminated. Metal layers on surface irregularities. According to the invention, the interconnection lines passing over the field regions may have a thickness of only 40 to 100 nm, the thickness of the second conductive layer. This allows the dielectric layer to be formed without gaps and to be more planar.

 During the photographic definition of the gate electrodes (FIGS. 3C and 4C) the interface between the resin layer 24 and the underlying conductive layer 52 is planar. Thus, the light 32 can no longer reflect towards the underlying region of the opaque part 30 of the mask 26 and reduce the size of the gate electrodes defined by this mask. The gate lengths are therefore not affected by the proximity between the transistor MS and the interface 18 with a field region. All transistors can therefore be defined with a minimum length.

 The upper flat surface presented in the photographic definition step avoids any thinning of the resin above the interface 18 between the active regions and the field regions, and also avoids any possible problem related to the depth of field of 1 photographic step since the entire surface is in the same plane.

 The planar conductive upper surface existing when defining the spacers (FIGS. 3E and 4E) avoids the formation of parasitic spacers 46. There is therefore no risk of rupture of the highly conductive layer 44 and no additional series resistance n 'is introduced above the interfaces 18.

 We therefore obtained a method of manufacturing semiconductor integrated circuits containing M06 transistors whose gates are defined with a constant and controlled length, regardless of the position of this ODS transistor in the circuit, and which have a flat upper surface to facilitate subsequent treatment steps while avoiding the problems associated with the formation of parasitic spacers that are encountered in the prior art.

 Many variants of the treatment steps according to the present invention can be envisaged, these variants providing at least certain advantages of the present invention.

 The field oxide can be obtained by power or deposited on the entire surface of the semiconductor substrate and then etched to define the active zones.

 The spacers 40 can be anis if one does not provide lightly doped source and drain regions 38.

 The highly doped source and drain regions 42 can be formed before the spacers 40.

 The highly conductive layer 44 can be severe before etching of the second conductive layer.

 Although a particular embodiment of the present invention has been described, various variants of this process will appear to the eye of the art in the field of the invention. The integrated circuits can be made of silicon, gallium arsenide or other semiconductor material, compatible materials being chosen for the gate and field dielectrics and for the conductive layers. One or both of the first and second conductive layers may be made of polycrystalline silicon or any other suitable material. The planarization of the first conductive layer 22 can be carried out by chemical mechanical polishing, sacrificial deposition and etching or other suitable process.

 The steps described can easily be incorporated into any process for manufacturing transistors) S or MOS / bipolar transistors.

Claims (7)

 1. Method for manufacturing MDS transistors for integrated circuits on a semiconductor wafer, including the following steps  forming field oxide regions (14) on an upper face of the wafer, to delimit active regions (12)  forming a gate oxide (20) on the active regions (12)  depositing a first layer of conductive material (22) at least on the active regions and the adjacent parts of the field oxide regions characterized in that it further comprises the following steps  planarize the resulting upper surface;  depositing at least a second layer of conductive material (24) on at least part of the first planarized layer of conductive material; and  engraving selected patterns on the first and second layers of conductive material.  2. Method according to claim 1, in which the planarization step is carried out by nXcenochemical polishing.  3. The method of claim 2, wherein the conductive material of the first layer is polycrystalline silicon and the chemical mechanical polishing is carried out using a slurry of potassium hydrcsyde and alumina in water.  4. Method according to claim 1, wherein the field oxide (16) has a thickness greater than 300 nm and the gate oxide (20) a thickness less than 12 nm.  5. MOS transistor formed in an integrated circuit having a gate electrode disposed on a gate oxide layer (20) and between two field oxide regions, characterized in that the gate electrode comprises first and second layers of conductive material (36, 54), the second layer at least partially covering the first layer, the camouflage surface between the first and second layers of conductive material being in the same plane as the adjacent upper surface of the region adjacent to field oxide.  6. The transistor of claim 5, wherein the first layer of conductive material (36) comprises polycrystalline silicon.  7. The transistor of claim 6, wherein the second layer of conductive material (54) comprises lin polycrystalline silicon.