FR2778109A1 - IMPLANTABLE MEDICAL DEVICE - Google Patents

Abstract

The present invention relates to an implantable medical device such as a pacemaker, a defibrillator etc. This device is characterized in that it comprises one or more circuits (C1 Cn) for performing at least one function for a predetermined period of time and a clock source (34) supplying clock signals (C11, C12 Cln ) at a plurality of clock frequencies, the clock source (34, 156, 204) being operatively connected so as to control the circuit (s) (C1 Cn) at a clock frequency such that substantially all of the predetermined time period is used to perform the function (s), the function (s) being completed just before the subsequent time period.

Description

The present invention relates to the power absorption of circuits

  integrated such as circuits used in medical devices and in particular implantable medical devices. It relates more particularly to the provision of an adjustable clock control and / or of multiple supply voltage levels for the operation of such circuits. Various devices require operation with low power absorption. For example, manual communication devices require such low power absorption and in particular the same is true of implantable medical devices. With regard to implantable medical devices such as for example implantable microprocessor cardiac devices, such as pacemakers and implantable defibrillators, these must be able to function with a low power absorption in order to increase the lifespan of the devices.

  batteries and the longevity of the devices.

  Generally such devices with low power absorption are designed using the technology called "complementary semiconductor metal oxide" (CMOS). CMOS technology is generally used because such technology has the characteristic of causing "static" power absorption

practically zero.

  The power absorption of CMOS circuits generally comprises two power absorption factors, namely a "dynamic" power absorption factor and a "static" power absorption factor. The absorption of static power is only due to the leakage current because the quiescent current of such circuits is zero. Dynamic power absorption is the dominant power absorption factor for CMOS technology. The dynamic power absorption is mainly due to the current required to charge internal and charging capacities

  during switching, i.e. for charging and discharging such capacities.

  The dynamic power (P) is equal to 1 / 2CVrDD2F, where C is the capacity of the node, F is the clock or switching frequency and VDD is the supply voltage for the CMOS circuit. As can be seen from the dynamic power calculation formula (P), the dynamic power absorption of CMOS circuits is proportional to the square of the supply voltage VDD. In addition, the power

  dynamic P is proportional to the clock or switching frequency.

  In accordance with the formula giving dynamic power absorption, it has been common practice, in the design of CMOS integrated circuits, to lower the supply voltage for a complete device (for example hybrid) or an integrated circuit, in order to operate the circuit with low supply voltages, in order to reduce the power absorption of such types of circuits. For example, in the device known as Medtronic Spectrax, around 1979, an integrated circuit was powered by a LiI cell instead of two cells. This reduced the supply voltage to

  2.8 volts from 5.6 volts, thereby reducing the current consumed.

  The voltages which must be greater than 2.8 volts have been produced by a voltage doubler or alternatively by a charge pump (for example output stimulation pulses). In addition, for example in the device known as Medtronic Symbios, around 1983, the logic circuit was supplied by a voltage regulator controlling the supply voltage of the integrated circuit to a supply of the "sum of thresholds" type. This regulator provided power to the

  integrated circuit (that is to say a voltage VDD) of several hundred millivolts au-

  above the sum of the thresholds of the channel n and of the channel p of the CMOS transistors constituting the integrated circuit. This regulator was of the self-calibrating type with respect to

  variations in the thresholds of the transistors due to manufacturing.

  Other devices have reduced power absorption in other ways. For example, various types of devices include analog stop blocks and / or stop clocks for logic blocks which are not used at particular times, thereby reducing the power absorbed. In addition, microprocessor devices have used a "puff clock" designed to operate a microprocessor at a very high clock frequency (for example typically 500-1000 kilohertz), for short periods of time, to take advantage of a "cycle factor" to reduce the average current drain. A clock of much lower frequency (for example generally 32 kHz) is used for other circuits and / or the processor when it is not operating in the high clock frequency mode, i.e. in puff clock mode. Many implanted devices based on a processor use the puff clock technique. For example, the implanted devices supplied by the companies Medtronic, Vitatron, Biotronic, ELA, Intermedics, Pacesetters, InControl, Cordis, CPI, etc., use puff clock techniques. By way of illustration, some examples which describe the use of a puff clock are

  given in US patents N 4,561,442, N 5,022,395, N 5,388,578 and N 5,154,170.

  FIG. 1 represents a graphic illustration of the variation of the energy / delay as a function of the supply voltage for CMOS circuits such as a CMOS inverter 10 represented in FIG. 2 by way of illustration. A supply voltage VDD is applied to the inverter 10 which is connected to the source of a PMOS field effect transistor 12. The PMOS transistor 12 has its drain connected to the drain of an NMOS field effect transistor 14 whose source is connected to ground. In this configuration, a voltage Vi applied to the two control electrodes of the transistors 12, 14 is inverted to provide an output voltage Vo. To simplify a clock cycle, a change in logic level is used to invert the input Vi at the output Vo. As illustrated in FIG. 1, the delay of the circuit logic increases notably when the supply voltage is reduced to almost one volt, as represented by the delay line 16 and the line of energy / delay 18. Therefore, reducing the supply voltage VDD to lower and lower levels is impossible in practice because of the need for a higher supply voltage when operating at a higher frequency is required. For example, in general, CMOS logic circuits must periodically assume functionality at a higher frequency, for example at a puff clock frequency. However, when the supply voltage VDD is decreased, such energy absorption is reduced by the square of the supply voltage VDD, as shown by the energy absorption line 20. Therefore , the speed requires a higher supply voltage VDD which is in direct conflict with a low

energy absorption.

  Other problems are also evident when lower VDD supply voltages are used for CMOS circuits. When a lower supply voltage is selected, static leakage current losses may occur, particularly at lower frequencies, due to increased static leakage current losses. Various techniques aimed at reducing the power absorption in devices are known and certain examples of these techniques are given in the

  US patents N 5,022,395, N 4,561,442, N 5,388,578 and N 5,154,170.

  The present invention has certain aims. In fact, various embodiments of the present invention provide solutions to one or more of the problems existing in the types of circuits according to the prior art having low power absorption, and in particular with regard to implantable medical devices. . These problems are as follows: CMOS circuits having too much dynamic power absorption lead to a reduction in the service life of the batteries; inability to effectively use low levels of the supply voltage; inability to provide adequate processing capabilities such as high-level processing capabilities including uplink / downlink telemetry, morphology detection, device initialization, while still providing processing capabilities low level such as detection of intrinsic beats, stimulation, telemetry at low speed, with the desired power absorption; and the impossibility of providing types of circuits operating at lower frequencies and therefore with lower power absorption compared to

  the use of higher speed clocks such as puff clocks.

  Compared to known techniques for reducing power absorption in various types of circuits, various embodiments of the present invention can provide one or more of the following advantages: reduced power absorption through the use of a voltage lower VDD supply; reduced power absorption due to decreased clock frequency for circuit types; increased longevity of circuits and in particular circuits of implantable devices; obtaining a potential reduction in the size of the product; minimization of losses due to static leakage current, i.e. absorption of static power; provision of types of multi-processor circuits and high performance processing circuits with additional possibilities of characteristics and functions as a result of the possibility of reducing power compared to other "required" characteristics and functions and obtaining a discount

notable from the current drain.

  Certain embodiments of the invention include one or more of the following features: operation of circuits to assume a desired function (generally assumed in a predetermined number of clock cycles) at a clock speed of a lower level or intermediate to complete the treatment adequately just in time before the next required functional process; use of practically the whole of a predetermined period of time (for example based on physiological events such as during a blindness interval, a higher cadence interval, an escape interval, a refractory interval and a communication protocol between pulse generator / programmer etc.) to perform a function at a clock speed such that the function is completed just before any subsequent required functional process; providing one or more voltage sources or a voltage source operable to deliver one or more supply voltages adjusted for various functions of a single integrated circuit; operational connection of a clock source to at least two circuits so that different circuits can operate at different clock frequencies; adjusting the supply voltage levels connected to one or more circuits based on the clock frequencies used to control the operation of the circuits; adjusting the bias of a circuit control electrode based on the supply voltage level applied to the circuit; supplying various supply voltage levels to a processing circuit according to the function to be assumed by this processing circuit; controlling the operation of a processing circuit at different clock frequencies depending on the function performed by the processing circuit; "on-the-fly" modification of the supply voltage level as required by specific circuit synchronization functions that are required for various circuits or the functionality of a frequency-based processing circuit

  clock used for controlling the operation of such a circuit.

  Various embodiments of the present invention will be described below, by way of nonlimiting examples, with reference to the appended drawings in which: FIG. 1 is a graphic illustration illustrating the variation of the energy / delay as a function of the supply voltage for the operation of a

CMOS circuit.

  FIG. 2 represents a CMOS reverser according to the prior art which

  is used as a building block in many types of CMOS circuits.

  Figure 3 is a block diagram of a "just in time" clock system

according to the present invention.

  Figures 4A to 4C show timing illustrations

  intended to be used for the description of the "just in time" clock system of the

figure 3.

  Figure 5 is a block diagram of a system producing voltages

  multiple feed according to the present invention.

  Figure 6 is a block diagram illustrating a system providing a variable supply voltage according to the present invention, Figure 7 is a block diagram of a processing circuit controlled by

  a clock according to the present invention.

  FIG. 8 is a diagram illustrating a medical device implantable in a body. Figure 9 is a block diagram of a pacemaker circuit intended to be used to illustrate one or more embodiments of this

invention.

  Figure 10 is a block diagram of an implantable pacemaker / defibrillator usable to illustrate one or more embodiments of the present invention. FIG. 11 is a block diagram illustrating a system for processing digital signals with variable clock / variable supply voltage according to the present invention. The present invention will be described first of all in general with reference to FIGS. 3 to 7. The invention will then be described with reference to configurations of implantable medical devices represented by way of illustration on the

Figures 8 to 11.

  FIG. 3 is a general block diagram of a "just in time" clock system 30. The "just in time" clock system 30 comprises an integrated circuit 32 and a clock source 34. The integrated circuit 32 comprises a plurality of circuits CI, C2, C3, Cn. When it comes into operation, each circuit is capable of assuming one or more functions of the circuit. A function is defined as any operation intervening on one or more inputs, during a plurality of cycles, resulting in an output. Generally, the functions assumed by the various circuits C1-Cn are executed in a predetermined number of clock cycles. Clock source 34 can operate to provide clock signals at a plurality of frequencies

  generally indicated by CI 1, C12 ... Cln.

  The circuits C1-Cn of the integrated circuit 32 can comprise circuits with discrete function (that is to say logic circuits intervening on one or more inputs to assume a particular function in order to deliver one or more outputs from these circuits ), such as circuits operating on an input from a sensor in order to provide a representative signal to another functional circuit, to a transmitter-receiver circuit, a conversion circuit, etc. In addition, the circuits Cl - Cn can be data processing circuits capable of assuming multiple functions under the control of a program or else these C1-Cn circuits can materialize software functions / routines which must be completed before a subsequent event or before departure of the next function. For example, as will be described later in connection with illustrative embodiments of implantable medical devices, these circuits may include digital signal processing circuits, a circuit used for telemetry up / down link, a circuit of R morphology detection, an arrhythmia detection circuit, a monitoring circuit, a

  stimulation, microprocessors etc ....

  The functions assumed by each of the Cl-Cn circuits must typically be completed within a particular period of time before a subsequent functional process is initiated. For example, a logic circuit may execute a function in a predetermined period of time in order to deliver an output required by another circuit, or else a function may have to have been executed by the processing circuit for a particular period of time as a result of the need for further processing to be performed by the processing circuit. For example, in an implantable medical device, treatment to complete a particular function may require to be performed in a portion of a particular time interval such as a blinding interval, a higher frequency interval, an interval d escape or a refractory interval of a cardiac cycle or even during a protocol

  pulse generator / programmer.

  The clock source 34 can be configured in any way to output clock signals at a plurality of frequencies. Such a clock source 34 can comprise any number of clock circuits each of which delivers a single clock signal at a particular frequency, the clock source 34 can also comprise one or more adjustable clock circuits for delivering clock signals in a continuous range of clock frequencies, and / or the clock source 34 may include a clock circuit which is capable of supplying clock signals at discrete clock frequencies at the difference from a continuous range. For example, the clock source 34 may include oscillators, clock dividers, timers, clock control circuits or other circuit elements required to provide clock signaling in accordance with the present invention. Preferably, the clock source 34 is configured as a low frequency clock

  continuously oscillating and a high frequency clock with on / off control.

  The operation of the just-in-time controllable clock of the "just-in-time" clock system 30 of Figure 3 will now be described with reference to Figures 4A to 4C. As illustrated in Figure 4A, the time period x represents the period of time during which a circuit, for example one of the Cl-Crin circuits, must have completed one or more functions. This same time period x is represented in FIG. 4B. time x can be any number of different time periods. For example, the time period can be the length of time that a processing circuit must perform a particular detection function due to the need to provide an output of detection at a certain time, it may be a period of time required for a particular function to be completed by a certain logic circuit in order to provide an output at a suitable time for a detection circuit. digital signal processing, it can be a period of time to complete a routine of the software etc ... In addition, the period of time x can correspond,

  for example, to a heart cycle or part of it.

  As illustrated in Figure 4B, following conventional processing, circuit functions were typically assumed at a puff cycle frequency and therefore the function assumed required a period of time 60. Therefore, only one small time interval (i.e. time period 60) of the entire time period x was used to perform the function or functions requiring n time cycles to be completed. In such a case, puff clocks were traditionally set to a notably high clock frequency, for example 500 to 1000 kHz, for such short periods of time, in order to take advantage of a "cycle factor" to reduce the average current drain. However, such high clock frequencies may not

  not be required to perform such or all functions.

  With the "just in time" clock system according to the present invention, as illustrated in FIG. 4A, practically the entire time period x is used to assume the function or functions which are completed in n cycles . In other words, the clock frequency, for example one of the frequencies Cll-Cln, for the circuit executing the function (s) during the time period x is adjusted so that the function (s) are completed in the maximum time which is available for the execution of such functions, that is to say that the clock frequency has its lowest possible value. In other words, a low frequency clock is used in such a way that the function or functions are executed "just in time" for the execution of the functionality of the other circuit or of the other routine. In this "just in time" mode, the clock frequency used to control the execution of such functions by the particular CMOS circuit is lowered which results in reduced power absorption by the CMOS circuit and in accordance with dynamic power calculations, the lower frequency results in a proportional reduction in the absorbed power. With the lowering of the clock frequency, the integrated circuit 32 including the various circuits C1-Cn can be designed so as to operate at a lower frequency, unlike the puff frequency, and also at various other frequencies

as needed.

  Preferably, as is used at present, the use of an almost entirely predetermined period of time may result in the completion of one or more functions executed before the end of the period of time x, as well as is represented by the remaining time period 55 in Figure 4A. This period of time

  remaining 55 is preferably close to 0 seconds.

  FIG. 4C represents an example of a time course in the case of a processing circuit which assumes multiple functions. For example, the cycle

  a patient's heart is shown in Figure 4C as the time period x.

  During time period 71, i.e. during a QRS complex of the heart cycle, high speed processing is performed at a high clock frequency compared to a lower clock frequency which is used to control the operation of the processing circuit during the period of time y. During this period of time y, when the processing circuit operates at a lower clock frequency, such a lower clock frequency can be adjusted in such a way that the functions executed during z cycles are practically in the whole of the maximum period of time which is available for such processing, i.e. in the period of time y. Again, a small remaining period of time 75 of the time period x of the cardiac cycle may exist. Such a period of time may be, for example, in the range of from about 1.0 milliseconds to about 10.0 milliseconds when the heart cycle is in the range of from about 400 milliseconds to about

1200 milliseconds.

  FIG. 5 is a general block diagram of a system 100 producing multiple supply voltages in which one or more supply voltages are available and regulated for their application in various circuits in an integrated circuit. The system 100 delivering multiple supply voltages comprises an integrated circuit 102 and a supply voltage source 106. The integrated circuit 102 comprises circuits CI, C2, C3 ... Cn. The supply voltage source 106 can operate to deliver a plurality of supply voltages V1, V2 ... Vn. Each supply voltage from the supply voltage source 106 is adjusted to be applied to one or more of the circuits C1-Cn. As illustrated, the supply voltage VI is applied to the circuit C1, the supply voltage

  V2 is applied to circuits C2 and C3 etc ...

  The setting of the supply voltages V1-Vn applied to the particular circuits Cl1-Cn, depends on the frequency at which the circuits C - Cn must operate. For example and as described above, the logic delay of such CMOS type C1-Cn circuits increases sharply when the supply voltage is reduced to almost 1 volt. If such a logic delay is tolerable, the supply voltage applied to a particular circuit notably reduces the power absorption of this particular circuit since the energy absorption is reduced in proportion to the square of the supply voltage VDD . However, if such a logic delay is not tolerable, for example if the logic circuit assumes a function which must be completed in a particular period of time, the reduction of the supply voltage VDD

  applied to such a circuit will be limited according to the acceptable logical delay.

  However, the supply voltage VDD for any particular circuit can be reduced to as low a value as possible while still meeting the requirements

in terms of speed.

  The integrated circuit 102 can include various circuits C1-C like those described with reference to FIG. 3. The supply voltage source 106 can be produced using a variety of components and it can include any number of voltage sources among each of which provides a single supply voltage level, it may include one or more voltage sources set to deliver supply voltage levels in a continuous range of levels and / or it may include a voltage source that can operate so as to deliver discrete supply voltage levels instead of levels in a continuous range. The supply voltage source 106 may comprise a voltage divider, a voltage regulator, a charge pump or any other element for supplying the supply voltages V1-Vn. Preferably, the supply voltage source 106 is

  configured as a charge pump.

  Traditionally, the supply voltage VDD is generally in the range from about 3 volts to about 6 volts. Preferably, according to the present invention, the supply voltages V1-Vn are in the range from approximately

  1 volt to around 3 volts depending on the CMOS technology used. As a result of the reduction in the supply voltage VDD, the supply voltage

  VT threshold for circuits is also reduced. For example, with supply voltages in the range from about 3 volts to about 6 volts, the threshold voltage for CMOS devices is generally in the range from about 0.8 volts to about 1, 0 volts. Preferably, in implantable medical devices, lithium batteries are used as implantable batteries. Such lithium batteries generally have a voltage in the range from about 2.8 volts to about 3.3 volts and generally the CMOS circuit has an associated threshold voltage of about 0.75 volts. By reducing supply voltages below 2.8 volts, the threshold voltages for CMOS devices can be reduced to the point of being in the range of about 0.2 volts to about 0.3 volts . There are commonly different types of ultra-low power logic operating at a supply voltage as low as about 1.1 volts, such as the types of logic for microprocessors and

  types of portable products. Through the use of suitable supply voltages V1-

  Vn, types of low power or ultra low power logic can be used for at least some of the various Cl -Cn circuits of integrated circuit 102. Other circuits may require higher supply voltages. As a result of the use of lower threshold levels due to lower supply voltages, the losses of static power absorption undesirably increase by several

orders of magnitude.

  Consequently, the system 100 delivering multiple supply voltages may optionally further comprise a source of bias of rear control electrodes 130 for delivering bias voltages BV1-BVn to the circuits.

  C1-Cn of the integrated circuit 102. In general, the bias voltages BV1-

  BVn of the rear control electrode depend on the supply voltage V1-Vn applied to the circuits C1-Cn in order to adjust the threshold voltages for the devices of the circuits C1-Cn. For example, the threshold voltage VT for the CMOS devices of the circuit can be set to a lower value by providing a bias voltage from the rear control electrode to the particular circuits to which the lower supply voltage is applied. In addition, for example, if circuit C1 is supplied with a lower supply voltage VI, a bias voltage BV1 of the rear control electrode can be optionally applied to circuit C1 in order to adjust the threshold voltage VT for CMOS devices at a higher threshold voltage value VT. In this way, the static leakage current losses can be minimized because the equivalent higher threshold voltage has been restored. In addition, a wider range of supply voltages is possible because the adjustment of the rear control electrode allows adjustment of the threshold allowing operation at high / low speed and eliminating leakage from the static current drain. The bias voltage of the rear control electrode can be supplied, for example, by a fixed voltage source (i.e. a charge pump) connected to the rear electrode by a contact. According to a variant, it is possible to use a diagram with polarization of the active body in which the voltage source is selectable

  or adjustable within an appropriate range.

  The rear electrode voltages can be applied in any known manner. For example, the application of the bias voltages of the rear electrode is described in particular in US patents N 4,791,318, N 4,460,835, N05,610,083 and

N 5,185,535.

  FIG. 6 is a general block diagram of a system 150 with variable supply voltage / variable clock. The system 150 comprises an integrated circuit 152, a clock source 156, a supply voltage source 154 and a clock / supply voltage interface 155. The supply voltage source 154 can operate to deliver a plurality of supply voltages V1, V2 ... Vn to a plurality of circuits C1, C2, C3 ... Cn. In addition, the clock source 156 of the system 150 can operate to output clock signals to a plurality of frequencies ClI, C12 ... Cln. The circuits CI1-Cn are similar to those described with reference to FIG. 3, the clock source 156 is similar to the clock source 34 as described with reference to FIG. 3 and the supply voltage source 154 is similar to the supply voltage source 106 as described with reference to FIG. 5. However, in the system 150 with variable supply voltage / variable clock, a clock / voltage interface 155 is used to adjust "to the flight "the supply voltages V1-Vn applied to circuits C1-Cn as required by synchronization functions

  specific requirements for C1-Cn circuits.

  By way of example, the circuit C1 can be a particular logic circuit which must execute one or more particular functions. However, these functions may have to be executed in a first period of time at a first clock frequency and for a second different period of time at a second clock frequency, to assume this function in the allocated time and first and second periods of respective times. In other words, one period of time is shorter than the other and therefore functions which require execution over a certain number of cycles must be executed at a higher clock frequency if they are to be

  completed in a period of time which is shorter than another period of time.

  In such an example, according to the present invention, the clock / voltage interface 155 detects the clock signal applied to the circuit C1 during the first period of time during which the higher frequency clock signal is used and by Consequently, it supplies the supply voltage source 154 with a signal intended to select and apply a certain supply voltage corresponding to the higher clock frequency. After that, when the lower clock frequency is applied to the IC circuit during the second period of time, the clock / voltage interface detects the use of the lower clock frequency and applies a signal to the voltage source. supply 154 to apply a certain supply voltage corresponding to the lower clock frequency, with a view to its application to the circuit Ci. Furthermore, the circuit C2 may for example be a CMOS processor which may also have a frequency clock and supply voltage settings

  correspondent performed "on the fly". Such a system will become clear from the description

  which will follow made with reference to FIG. 7.

  FIG. 7 is a general block diagram of a processing system 200 controlled by a clock according to the present invention. The processing system 200 controlled by a clock comprises a processor 202 (for example a CMOS microprocessor or a CMOS digital signal processor), a clock source 204, a supply voltage source 206, a voltage regulator 212, a regulator interface 210, a clock control 208 and an optional source 214 for bias voltage of the rear control electrode. In the same way as has been described with reference to FIG. 6, the supply voltage applied by the source 206 to the processor 202 is modified "in flight" as required by the

  specific circuit synchronization requirements.

  Generally, processor 202 operates under the control of clock source 204. Depending on the processing capacity required, clock source 204 can operate processor 202 at any of several frequencies clock. These clock frequencies are selected by the clock control 208. The clock control 208 may be part of any synchronization and control hardware and / or any synchronization and control software used for controlling the operation of processor 202 as part of a larger system. For example, such a clock command may take the form of a digital controller / timer circuit to execute a clock command.

  synchronization of an implantable medical device.

  Processor 202 can perform any number of functions appropriate for the device in which it is used, High frequency processing capabilities (i.e., approximately 250 kHz to approximately 10 MIz), processing capabilities at low frequency (that is to say from approximately 1 Hz to approximately 32 kHz) and processing capacities at frequencies between these limits are to be envisaged according to the present invention. For the sake of simplification, the operation of the processing system 200 controlled by a clock will be described in the case of a processor 202 performing only two different functions, each of them for a respective predetermined period of time. For example, with respect to an implantable medical device such as a pacemaker, during the first period of time, a high-level processing function requiring a relatively high clock frequency may include a function such as telemetry to ascending / descending link, morphology detection, initialization, arrhythmia detection, R wave detection in far field, electromagnetic interference detection, retrograde conduction, etc. In addition, functions low frequency processing may include a function such as intrinsic beat detection, stimulation, low speed telemetry, transfer

  data telephone, remote monitoring, battery control, etc.

  When the processor 202 is to execute, for a predetermined period of time, high-frequency processing functions, a relatively high clock frequency, ranging for example from 250 kHz to 10 MHz, can be supplied by the clock source 204 for the operation of the processor 202. The interface regulator 210 detects the higher clock frequency applied to the processor 202 for its operation during the high-frequency processing function and it applies a control signal to the voltage regulator 212 to ensure regulating the supply voltage source 206. The supply voltage source 206 can operate under the control of the voltage regulator 212 so as to deliver a supply voltage within a predetermined range which preferably ranges from about 1.1 volts to approximately 3 volts. When a high clock frequency is used for the operation of the processor 202, for the high frequency processing functions, the supply voltage source 206 generally applies a supply voltage, included in the range higher of the preferred supply voltages,

  CMOS devices of processor 202.

  Furthermore, when the processor 202 must execute processing functions at low frequency during the predetermined periods of time, the clock command 208 signals to the clock source 204 to have to apply a lower frequency for the operation of the processor 202. In doing so, the regulator interface 210 detects that the lower frequency is being used for the operation of processor 202 and it issues a control signal to the voltage regulator 212 in order to adjust the voltage source. supply 206 so that a lower supply voltage, located at the lower end of the preferred range of voltages

  applied to the CMOS devices of processor 202.

  Those skilled in the art will understand that any processing capacity at an intermediate frequency can be obtained between the high frequency and low frequency processing capacities described above and that the present invention is in no way limited to the processing of only two clock frequencies and only two corresponding supply voltages. On the contrary, multiple levels of processing capacities can be obtained, according to the present invention, with the associated clock frequencies and the corresponding supply voltages.

applied to processor 202.

  FIG. 4C illustrates the operation of an embodiment of the processing system 200 controlled by a clock. As illustrated in this figure, during the entire heart cycle spanning the predetermined time period x, a high frequency is used to control the operation of the processor 202 during the time period 71 of the time period x of the cardiac cycle, for example during the treatment of the QRS complex. After that, a lower clock frequency is used during the time period y for controlling the operation of the processor 202, for performing any other functions among a number of other different functions, such as functions of differentiation between cardiac events and electromagnetic interference. During the operation of the processor 202 at the higher clock frequency, during the time period 71, a higher supply voltage, coming from the supply voltage source 206, is applied to the CMOS devices of the processor 202. Likewise, during operation of processor 202 at the relatively lower clock frequency, a lower supply voltage from the supply voltage source 206 is applied to the CMOS devices of processor 202 during the time period

  being part of the time period x of the global cardiac cycle.

  Furthermore, as illustrated in FIG. 7, an optional source 214 of bias voltage for the rear control electrode can be used to dynamically adjust the voltage threshold VT of the CMOS devices of processor 202 according to the clock frequency applied to processor 202 by clock source 204. The regulator interface 210 detects the clock frequency used to control the operation of processor 202 and controls the voltage level of the voltage source 214 of polarization of the rear control electrode to be applied to the CMOS devices of processor 202. The dynamic adjustment of the threshold voltage can be carried out in the form of an adjustable or selectable voltage source using for example a charge pump and a regulator. The bias voltage of the rear control electrode and the voltage of the "normal" control electrode provide bias or control electrode voltage to the transistor. By adjusting the voltage of the rear control electrode, the "apparent" voltage is

  increased which results in a corresponding reduction in leakage current.

  FIG. 8 is a simplified diagram of an implantable medical device 260 for which the present invention can be used. The implantable device 260 is implanted in a body 250 near a human heart 264. The implanted medical device is connected to the heart by conductors 262. In the case where the device 260 is a pacemaker, the conductors 262 are conductors of stimulation and detection ensuring the detection of electrical signals resulting from the depolarization and repolarization of the heart 264 and they supply stimulation pulses in the vicinity of their distal ends. The implantable medical device 260 can be any implantable pacemaker such as those described in US patents N 05 158 078 and N05 144 949. The implantable medical device 260 can also be a pacemaker / defibrillator (PCD) corresponding to the any of the various devices

  commercially available PCD implantable devices, one of which is briefly described

  presently with reference to FIG. 10 and is described in detail in US Patent No. 5,447,519. In addition to the PCD apparatus described in US Patent No. 5,447,519, the present invention can be implemented in conjunction with apparatuses PCDs such as those described in US Patents N 5,545,186, N 5,354,316, N 5,314,430, N05 131,388 and N 4,821,723. These devices can be employed using the present invention in that such devices can use or be modified with circuits and / or

  systems according to the present invention.

  The implantable medical device 260 can also be a nerve stimulator or an implantable muscle stimulator such as those described in US patents N 5 199 428, N05 207 218 and N 5 330 507, or even an implantable monitoring device such as that described in US Patent No. 5,331,966. The present invention can find a wide field of applications for any form of electrical device which uses one type of CMOS circuit and is particularly advantageous when low power is desired, more especially in devices

implantable medical devices.

  In general, the implantable medical device 260 includes a hermetically sealed envelope which includes an electrochemical cell such as a lithium battery, a

  CMOS circuit which controls the operation of the device, and a transmitting antenna-

  telemetry receiver and a circuit that receives downlink telemetry commands and that transmits data stored in an uplink telemetry link to an external programmer. The circuit can be realized in the form of discrete logic and / or it can comprise a system based on a microcomputer with a

analog / digital conversion.

  It should be understood that the scope of the present invention is not limited to electronic particularities and particular operations of particular implantable medical devices and that it can be used in conjunction with various implantable devices. Furthermore, the present invention is not limited to implantable medical devices including only a single processor but that it can also be applied.

  well to devices with multiple processors.

  Figure 9 is a block diagram illustrating the components of a pacemaker 300 according to an embodiment of the present invention. The pacemaker 300 has an architecture based on a microprocessor. However, the pacemaker 300 shown by way of illustration in FIG. 9 is only an example of such devices and it will be understood that it can be produced with an integrated circuit architecture, based on logic, if desired, as any which system based on

a microprocessor.

  In the embodiment given by way of example and shown in FIG. 9, the pacemaker 300 is preferably programmable by means of an external programming unit (not shown in the figures). One such programmer suitable for the purposes of the present invention is the programmer known as the Medtronic Model 9790 commercially available. The programmer is a device based on a microprocessor which supplies a series of coded signals to the pacemaker 300 by means of a programming head which transmits coded radio frequency signals to the antenna 334 of the pacemaker 300 in accordance with a system of telemetry such as that described in US Pat. No. 5,127,404. It will however be understood that any programming methodology can be used provided that the desired information is transmitted to the stimulator

heart and from it.

  The pacemaker 300 which is shown in Figure 9, is electrically coupled to the patient's heart 264 by leads 302. The lead 302a, having an electrode 306, is connected to a node 310 in the pacemaker circuit 300, by the intermediary of an input capacitor 308. The conductor 302b is connected to a pressure circuit 354 of an input / output circuit 312, in order to supply to the circuit 354 a pressure signal coming from a sensor 309. The pressure signal is used to determine the metabolic requirements and / or cardiac output of a patient. In addition, an activity sensor 351, such as a piezoceramic accelerometer, provides sensor output to an activity circuit 352 of the input / output circuit 312. The output of the sensor varies depending on a parameter. measured which indicates a patient's metabolic requirements. The input / output circuit 312 contains circuits for communicating with the heart 264, with the activity sensor 351, with the antenna 334 and with the pressure sensor 309 and the circuits for applying stimulation pulses to the core 264 in order to control its rhythm as a function of these pulses, under the control of algorithms implemented in the software in a microcomputer 314. The computer 314 preferably comprises an on-board circuit 316 which includes a microprocessor 320, a circuit system clock 222 and on-board memory 324 and read-only memory 326. In this embodiment given by way of illustration, an independent circuit 328 comprises a random access memory and read only memory unit. The on-board circuit 316 and the independent circuit 328 are each connected, via a communication bus 330, to a digital circuit

controller / timer 332.

  According to the present invention, the circuits represented in FIG. 9 are electrically supplied by an implantable supply voltage source 301, suitable (for example a voltage source generally represented in FIGS. 1 to 7). For the purpose of clarification, the connection of the supply voltage source 301 to the various circuits of the pacemaker 300 is not shown in the figures. In addition, the circuits which can operate under the control of a clock signal shown in FIG. 9, operate, according to the present invention, under the control of clock source 338. In order to clarify, the coupling of such clock signals, coming from clock source 288 (for example a clock source indicated generally in FIGS. 1 to 7) to the CMOS circuits of

  pacemaker 300 is not shown in the figures.

  The antenna 334 is connected to the input / output circuit 312 in order to allow up / down telemetry via the radiofrequency transmitter and receiver unit 336. The unit 336 can correspond to the logic telemetry and program described in US Patent No. 4,556,063 or that described in the patent

US N 5,127,404 cited above.

22 2778109

  A VREF reference voltage and bias circuit 340 produces a stable voltage reference and bias currents for circuits in the input / output circuit 312. A unit 42 of analog / digital converters and multiplexers digitizes analog signals and voltages to produce intracardiac telemetry signals "in real time" and replacement of end-of-life batteries. A circuit 341 for restoring the electrical supply operates in

  as a means of re-establishing the circuit.

  Operation commands to control the timing of the pacemaker 300 are applied by the bus 330 to the digital controller / timer circuit 332 in which digital timers and counters establish the overall escape interval of the pacemaker 300 as well as various refractory windows , deletion and other synchronizations to control the operation of the peripheral components arranged in the input / output circuit 312. The digital controller / timer circuit 332 is preferably connected to a detection circuit 345 and to an electrogram amplifier. 348 for receiving amplified and processed signals which are detected by the electrode 306 disposed on the conductor 302a. Such signals are representative of the electrical activity of the patient's heart 264. A detection amplifier 346 of circuit 345 amplifies the detected electrocardiac signals and delivers an amplified signal to a peak detection and threshold measurement circuit 347. This circuit 347 in turn provides an indication of the detected peak voltages and voltages. threshold values of the detection amplifier on a conductor 357 leading to the digital controller / timer circuit 332. A signal from the amplified detection amplifier is also supplied to a comparator / threshold detector 349. The detection amplifier 332 corresponds to the one described in the

U.S. Patent No. 4,379,459.

  The electrogram signal supplied by the electrogram amplifier 348 is used when the implanted device 300 is being interrogated by an external programmer (not shown) in order to transmit, by uplink telemetry, a representation of an analog electrogram of the electrical heart activity of a

  patient. Such functionality is described, for example, in US Pat. No. 4,556,063.

  An output pulse generator and amplifier 350 deliver stimulation pulses applied to the patient's heart 264 via the coupling capacitor 305 and the electrode 306, in response to a signal

  stimulation trigger delivered by the digital controller / timer circuit 332.

  The output amplifier 350 can generally correspond to the output amplifier described in US Pat. No. 4,476,868. The circuits of FIG. 9 which constitute an assembly of the CMOS type capable of operating in accordance with the present invention include processor 320, digital controller / timer circuit 332, random access memory 324, read-only memory 326, read-only memory / read-only memory 328 and

  the analog / digital / multiplexer 342 unit.

  Figure 10 is a block diagram from U.S. Patent No. 5,447,519

  which represents an implantable device 400 of the PCD type (pacemaker-

  cardioverter-defibrillator) in which the present invention can be used in practice. This diagram is an illustration which should be considered as being only an example of a device in which the invention can be incorporated and not as limiting the scope of the present invention. As previously described, other implantable medical devices, having functional organizations in which the present invention can be used, can also be modified in accordance with the present invention. For example, the present invention can also be used in conjunction with implantable PCD devices such as those described in the

  US patents N 4,548,209, N 4,693,253, N 4,830,006 and N 4,949,730.

  The illustrated PCD device 400 is provided with six electrodes 401,402,404,406,408 and 410. For example, the electrodes 401 and 402 can be a

  pair of closely spaced electrodes that are located in the ventricle of the heart 264.

  The electrode 404 may correspond to a remote indifferent electrode situated on the envelope of the implantable PCD device 400. The electrodes 406, 408 and 410 may correspond to defibrillation electrodes with large surface area located on

  conductors ending in the heart 264 or epicardial electrodes.

  Electrodes 401 and 402 are shown as being wired to a near-field R wave detector circuit (i.e., closely spaced electrodes) comprising a bandpass filter amplifier 414, a threshold-adjusted circuit 416 automatically (to provide an adjustable detection threshold according to the amplitude of the measured R wave) and a comparator 418. A ROUTE 464 signal is produced each time the signal detected between the electrodes 401 and 402 exceeds a detection threshold defined by circuit 416 with automatically adjusted threshold. In addition, the gain of the amplifier 414 is adjusted by a timer and stimulator control circuit 420. The detection signal 464 is used for example to establish the synchronization windows and to align data of successive waveforms for the purpose of detecting the morphology. For example, the detection signal 464 can be routed through the stimulator timer and control circuit 420, on a bus 440, to a processor 424 and it can act as an interrupt for this processor 424 so that '' a particular routine of operations, such as for example detection

  morphology, discrimination functions, or started by processor 424.

  A switching matrix 412 is used to select electrodes available under the control of processor 424, via a data / address bus 440, such that the selection includes two electrodes used as a pair of electrodes far field (i.e. widely spaced electrodes), together with a tachycardia / fibrillation discrimination function (function to distinguish between tachycardia, i.e. abnormally fast heart rate, and fibrillation, that is, uncoordinated and irregular heartbeat, so as to apply appropriate therapy). The far field electrogram signals from the selected electrodes pass, through a bandpass amplifier 434, to and in a multiplexer 432 where they are converted into digital data signals by an analog / digital converter 430 for storage. in a random access memory 426 under the control of a circuit 428 for direct access to the memory. For example, a series of

  Electrogram complexes spanning several seconds can be performed.

  According to the present invention, the circuits represented in FIG. 10 are supplied by a source of supply voltage suitable for batteries 490, implantable (for example a voltage source generally represented in FIGS. 1 to 7). For the purpose of clarification, the connection of the supply voltage source 490 to the various circuits of the PCD device 400 is not shown in FIG. 10. In addition, the circuits that can operate under the control of a signal clock and which are shown in Figure 10, operate, according to the present invention, under the control of a clock source 491. For clarification purposes, the connection of clock signals from the clock source 491 such as a clock source generally represented in FIGS. 1 to 7, to the circuits

  CMOS of the PCD 400 device is not shown in Figure 10.

  The appearance of a ROUTE signal 464 for detecting an R wave is communicated to processor 424 in order to initiate a morphology analysis, by this processor 424, on the waveforms with a view to selecting a therapy. for the heart 264. For example, the processor can calculate the cumulative variability from one beat to the next beat of the heart 264, the time intervals separating the detections of an R wave and various other functions such as those stated in the numerous references including those already mentioned above and various other references

  relating to implantable PCD devices.

  Other portions of the PCD 400 device of Figure 40 are dedicated to the provision of cardiac stimulation, cardioversion and defibrillation therapies. With regard to cardiac stimulation, the pacemaker control and timing circuit 420 includes programmable digital counters which control the basic synchronization intervals associated with cardiac stimulation, including stimulation blanking intervals, refractory periods during which the detected R waves are ineffective in restarting the synchronization of the escape intervals, etc. The durations of such intervals are typically determined by the processor 424 and communicated to the circuit 420 for controlling and delaying the stimulator via the address / data bus 440. In addition, under the control of the processor 424, the circuit 420 for controlling and timing the pacemaker also determines the amplitude of such cardiac stimulation pulses and a circuit 421 for outputting the stimulation pulses provides these impulses

in the heart.

  In the event that a tachyarrhythmia (i.e., tachycardia) is detected and a tachyarrhythmia stimulation therapy is desired, appropriate timing intervals to control the production of tachyarrhythmia stimulation therapies are loaded from the processor 424 to and in the stimulator control and timing circuit 420. Likewise, in the case where the production of a cardioversion or defibrillation pulse is required, the processor 424 uses the counters and the stimulator control and timing circuit 420 to control the timing of such cardioversion pulses and defibrillation. In response to the detection of a fibrillation or a tachycardia requiring a cardioversion pulse, the processor 424 activates a cardioversion / defibrillation control circuit 454 which initiates the charging of high voltage capacitors 456,458,460 and 462, via of a charging circuit 450, under the control of a high-voltage charging line 452. After that, the timing of the defibrillation or cardioversion pulse is controlled by the circuit 420 for controlling and timing the stimulator. Various embodiments of a system suitable for producing and synchronizing cardioversion and defibrillation pulses and for controlling the timing functions related thereto are described in more detail in US Patent No. 5 188 105. Other circuits for controlling the timing and production of cardioversion and defibrillation pulses are described in US Pat. Nos. 4,384,585, N 4,949,719 and N 4,375,817. In addition, circuits known controlling the timing and the production of pulses of antitachyarrhythmia stimulation are described in US patents N 4,577,633, N 4,880,005, N 4,726

380 and N 4,587,970.

  The selection of a particular electrode configuration for the production of the cardioversion or defibrillation pulses is controlled via an output circuit 448 under the control of the cardioversion / defibrillation control circuit 454, via a control bus 446. The output circuit 448 determines which of the high voltage electrodes 406, 408 and 410 will be

  used for the production of defibrillation or cardioversion pulses.

  The components of the PCD device 400 of FIG. 10 which are CMOS circuits capable of operating in accordance with the present invention, include the processor 424, the control circuits 420 and 454, the random access memory 426, the direct access circuit 428 in memory, the analog / digital converter 430 and the multiplexer 432. According to the present invention, the pacemaker 300 illustrated in FIG. 9 and the PCD device 400 illustrated in FIG. 10 can both be produced physically in accordance with the generalized embodiments which have been described previously with reference to FIGS. I to 7. First of all, as regards the pacemaker 300 of FIG. 9, the supply voltage source 301 of the pacemaker 300 can be produced physically as described with reference to FIGS. 1 to 7 and in the same way the clock source 338 of the pacemaker 300 can be re materially aligned as described with reference to FIGS. 1 to 7. Similarly, the clock source 491 of the PCD device 400 of FIG. 10 and the supply voltage source 490 of the PCD device 400 of FIG. 10 can be carried out materially in accordance with generalized forms of execution

  previously described with reference to Figures 1 to 7.

  As an illustrative example, the multiplexer and the analog / digital converter 342, the radio frequency transceiver 336, the digital controller / timer circuit 332 and various other CMOS circuits can be made to operate individually at different clock frequencies from of the source operate individually at different clock frequencies from the clock source 338. Likewise such circuits can operate with corresponding supply voltages which may be different for each of the circuits. Furthermore, the radiofrequency transceiver 336 can operate for a particular period of time (for example during an uplink) at a particular clock frequency originating from the clock source 338 and with a particular supply voltage. from the supply voltage source 301 corresponding to the aforementioned particular clock frequency. Furthermore, for a different period of time (for example during a downlink), the circuit 336 can operate at a totally different clock frequency and with a different supply voltage. The automatic adjustment of the telemetry parameters in certain circumstances is described in US Pat. No. 5,683,432. With reference to FIG. 10, the analog / digital converter circuit 430, the cardioversion / defibrillation control circuit 454 and others circuits such as random access memory 426, direct memory access circuit 428 and multiplexer 432 can also operate at different clock frequencies obtained from clock source 491 and with corresponding supply voltages and obtained from the supply voltage source 490. In addition, the telemetry circuit (not shown) can be used with the PCD device 400 of FIG. 10 and it can also operate at different clock frequencies obtained at from clock source 491 and with different corresponding supply voltages obtained from the supply voltage source n 490. Furthermore, the processor 424 can operate at different clock speeds depending on the function which is being executed by the processor 424, as described with reference to FIG. 7. For example, the detection of morphology at typical physiological frequencies (i.e. 50 to 150 beats per minute) can be performed at a first clock frequency and with a corresponding supply voltage while detection of an arrhythmia can be performed at a different clock frequency

  and with a corresponding supply voltage.

  FIG. 11 shows a digital signal processing system 500 with variable clock / variable supply voltage, which can be used in conjunction with certain circuits shown in FIGS. 9 and 10 or as variants thereof. For example, the digital signal processing system 500 according to FIG. 11 can be used in place of the activity circuit 352, the pressure circuit 354, the detection amplifier circuit 346 (for the detection amplifiers of the P wave, R wave and / or T wave) and it can also be provided with additional functionality with the use of a pseudo EKG 502 signal. Generally, a certain number of analog signals 499 such as for example pseudo EKG signals 502, a signal 503 from an activity sensor and a signal 504 from a pressure and start sensor, are supplied through respective amplifiers 505, 506 and 507. The amplified signals are applied to a multiplexer 510 which supplies them to an analog / digital converter 516 in a cyclic manner. The signals 502-504 can be introduced in cyclic form at different rates by cyclically selecting the outputs of the different amplifier-preamplifiers 505-507 as described in the patent application US N 08/801 335 which describes variable compression through sampling from an analog-to-digital converter. The analog / digital converter can also have conversion frequencies

  variables as described in US patents N 5,263,486 and N 5,312,446.

  An input / output interface 514 and program registers 512 are used, under the control of a timing circuit not shown, to control the application of the analog signals coming from the multiplexer 510 to the analog / digital converter 516 which applies the digital signals converted to a digital filter 518 to provide a waveform analysis processor 520 (a digital signal processor) a waveform suitable for such analysis. To reduce the power, the waveform analysis processor 520 is synchronized at different speeds, that is to say it is controlled "on the fly", according to the present invention, according to the requirements of the processing. For example, the waveform analysis processor 520 is in a high speed processing mode, at a relatively high frequency, only during a QRS complex while during the rest of the cardiac cycle, the processor 520 can operate. "at idle", at a much lower clock frequency. Such a treatment cycle has been described previously with reference to FIG. 4C. In addition to the lower clock speed used on different portions of the cardiac cycle, those skilled in the art will recognize when in agreement with the other aspects of the present invention, when the speed is reduced, the level of the supply voltage VDD can also be reduced correspondingly. We

  thus obtains reduced power absorption as described above.

  The present invention is compatible with various manufacturing technologies such as CMOS technologies of the silicon on isolator (SOI), silicon on sapphire (SOS) type, as well as the traditional CMOS silicon technologies. The present invention, as described herein, allows a technology for the use of digital signal processors allowing them to assume more functions as a result of how power absorption can be reduced for such processors. In addition, models based on multiple processors can also be realized physically as a result of reduced power absorption when supply voltages and clock frequencies are reduced for various

  functions performed by processors.

  In addition, since the power absorption is reduced, other functionality can be added to the devices so as to provide a device with added functions compared to the device previously absorbing more power. For example, the processor can perform various morphology detection functions such as the differentiation of retrograde P waves and antegrade P waves of an electrogram waveform, the differentiation of P waves with respect to waves. R at far field, the differentiation of AF-A tremor-AT of a sinus tachycardia, the differentiation of VT- VF-V tremor of SVT, the differentiation of cardiac signals from an electromagnetic interference etc ... For example, electromagnetic interference may occur from theft detectors,

  conductors, RF noise, myopotentials etc ...

  The previous particular embodiments illustrate the implementation of the invention. However, it will be understood that other means known to those skilled in the art can be used without departing from the scope of the invention. For example, the invention is not limited to the use of a clock source producing discrete clock frequencies but that these clock frequencies can vary continuously. In addition, the supply voltage source can be a source supplying only discrete supply voltages but also a source supplying a voltage varying continuously in a particular range, for example under the control of a voltage regulator. voltage. The present invention is also not limited to use in conjunction with pacemakers or PCD devices but it can also be applied in other fields such as telecommunications where low power absorption is desired. It can in particular be applied to other implantable medical devices such as an implantable defibrillator, an implantable pulse generator, an automatic implantable defibrillator, a brain stimulator, a neurostimulator, a sleep apnea stimulator, a pacemaker incontinence, a gastric stimulator and an implantable heart monitor. The present invention further encompasses the methods of implementing "just in time" synchronization principles and / or supply voltages.

  multiples which have been described previously.

Claims (15)

  1. An implantable medical device characterized in that it comprises one or more circuits (C1 ... Cn) capable of operating so as to execute at least one function during a predetermined period of time (x), this predetermined period of time (x ) extending between a previous period of time and a later period of time, at least one of the circuits (C1 ... Cn) being able to operate so as to complete the function or functions during a predetermined number of cycles clock source, and a clock source (34,156,204) providing clock signals (ClI, C12 ... Cln) at a plurality of clock frequencies, the clock source (34,156,204) being operatively connected so to control the circuit (s) (Cl ... Cn) at a clock frequency such that practically the whole of the predetermined period of time (x) is used to execute the function or functions, the function or functions being   completed just before the later time period.   2. Device according to claim 1 characterized in that the circuit or circuits (CI .. Cn) comprise at least a first logic circuit to execute a first function and a second logic circuit to execute a second function, the first logic circuit being able to operate to execute the first function for a first predetermined period of time (71) and the second logic circuit operable to execute the second function for a second predetermined period of time (y), and in that each of the first and second logic circuits operates at a different clock frequency such that substantially all of the respective first and second predetermined time periods (71, y) are used by the respective first and second logic circuits to execute the first and second respective functions.   3. Device according to claim 2 characterized in that the first predetermined time period (71) and the second predetermined time period (y) are   time periods based on physiological events.   4. Device according to claim 3 characterized in that at least one of the first and second time periods (71, y) is a time period selected from the following group of time periods associated with cardiac events including a suppression interval, a higher frequency interval, a blindness interval, a refractory interval and a pulse generator / programmer communication protocol. 5. Device according to claim 1 characterized in that the circuit or circuits (C1 ... Cn) comprise a processing device (202) operable to execute a plurality of functions, each function of the plurality of functions being executed during a associated predetermined period of time (x) preceding a subsequent period of time during which another function from the plurality of functions is performed, and the processing device (202) can operate to perform each of at least two functions of the plurality of functions at a different clock frequency such that substantially all of the associated predetermined time period (x) for each function is used to perform the functions before the later period of time during which another depending on the   plurality of functions is performed.   6. Device according to claim 5 characterized in that the associated predetermined time periods (x) are time periods based on physiological events.   7. Device according to claim 6 characterized in that at least one of the associated time periods is a time period selected from the following group of time periods associated with cardiac events including a suppression interval, an interval of higher frequency, an escape interval, a refractory interval and a pulse generator / programmer communication protocol. 8. Device according to claim 1 characterized in that it further comprises one or more supply voltage sources (154,206) for delivering one or more supply voltages (V1 ... Vn) and the source or sources supply voltage (154,206) are operationally connected to the circuit (s) (C1 ... Cn) so that a supply voltage (V1 ... Vn) is applied to at least one circuit (CI   Cn) by being a function of the clock frequency applied to the circuit (s) (C1 ... Cn).   9. Device according to claim 8 characterized in that the circuit (s) (C 1 ... Cn) comprise at least a first logic circuit to execute a first function and a second logic circuit to execute a second function, each of the first and second logic circuits operate at a different clock frequency and to each of the logic circuits is applied a different supply voltage (VI ... Vn) which is based on the different clock frequencies used to control the   first and second logic circuits.   10. Device according to claim 8 characterized in that the circuit (s) (C1 ... Cn) comprise a processing device (202) capable of operating so as to execute a plurality of functions, each of at least two functions of the plurality of functions is executed at a different clock frequency (ClI ... Cln) and the supply voltage (V1 ... Vn) applied to the processing device (202) is adjusted so that a first voltage power supply is used for the processing device (202) during the execution of one of the at least two functions and that a second supply voltage is used for the processing device (202) during the execution of the other function, the first and second supply voltages being applied being based on the different clock frequencies used for   controlling the processing device (202).   11. Device according to claim 10 characterized in that the first function is executed at a frequency relatively higher than the frequency for the execution of the second function and the level of the first supply voltage which is applied during execution of the first function is high compared to the level   of the second supply voltage.   12. Device according to claim 11 characterized in that the first function is a function selected from the group comprising the ascending / descending link of a high speed telemetry, the detection of morphology, the initialization of the device, the detection of arrhythmia, the detection of an R wave at field   distant, detection of electromagnetic interference and retrograde conduction.   13. Device according to claim 11 characterized in that the second function is selected from the group comprising the detection of intrinsic heartbeats, cardiac stimulation, low speed telemetry, transfer of trans-telephone data, the remote data surface and control of a battery. 14. Device according to claim 10 characterized in that it further comprises a multiplexer (510) for receiving a plurality of analog signals (502,503,504) and an analog / digital converter (516) for converting one or more of the analog signals into signals digital signals and for applying these digital signals to the processing circuit (520), the processing circuit (520) operating on the digital signals representative of at least one first analog signal among the plurality of signals (502, 503.504) in order to execute the first function and operating on the digital signals representative of at least one second analog signal among the   plurality of signals (502,503,504) to perform the second function.   15. Device according to claim 1 characterized in that the implantable medical device is selected from the group comprising a pacemaker, an implantable defibrillator, an implantable pulse generator, a pacemaker-defibrillator, an automatic implantable defibrillator, a pacemaker brain, neurostimulator, sleep apnea stimulator, incontinence stimulator, gastric stimulator and heart monitor implantable.