FR2659818A1 - BASIC SWITCH FOR SWITCHING ASYNCHRONOUS TIME MULTIPLEXED CELLS AND SWITCHING NETWORK USING THE SAME. - Google Patents

Abstract

Allowing broadcasting, this switch comprises a translated routing device (mcv), to receive from the label (RT) of a cell received on one of the inputs a reference number (IRN) and to translate it, to using a translation memory (mcv), in one or more output identities (AS), a management unit (UG) arranged in particular to receive marking cells containing routing information received on the inputs of the elementary switch and to write output identities accordingly in the translation memory, non-selective routing means comprising in particular distribution routing means (AS4) consisting in routing the received cell to all the outputs of the switch, routing mode selection means (CC), provided to receive from the tag (RT) of a marking cell received on one of the inputs a routing mode datum and to receive a semi-datum. permanent situatio n (SN) of the elementary switch and designed to selectively control, as a function of these data, the implementation of the routing device (mcv), that of the non-selective distribution routing means (AS4) and / or the sending this marking cell to said management unit (UG).

Description

 Basic switch for switching cells with asynchronous time division multiplexing and switching network by applying.

 The present invention relates to an elementary switch for switching asynchronous time-division multiplex cells enabling broadcasting, as well as a network for switching of asynchronous time-division multiplex cells in which such an elementary switch is included.

 The cells, also called packets, are digital information units comprising in particular a label containing an indication making it possible to identify the destination of the cell, as well as communication data.

 An elementary switch for switching cells with asynchronous time multiplexing comprises inputs, outputs, selective retransmission means, for retransmitting a cell received on one of its inputs, on one or more of its outputs as a function of routing data. associated with this cell, as well as, generally, retransmission control means determining the operating mode of said retransmission means.

 A switching network employing such an elementary switch comprises input ports and output ports, as well as elementary switches, arranged between the input ports and the output ports.

These elementary switches are arranged in one or more stages and interconnected by meshes. The input ports of the switching network are associated with the elementary switch inputs of a first stage, while the output ports are associated with the elementary switch outputs of a last stage. The outputs of the elementary switches of said first stage are coupled by meshes, possibly through intermediate stages of elementary switches, to the inputs of the elementary switches of said last stage.

 This network, in cell switching, has the function of routing cells, selectively, between, each time, an input port of the network and at least one output port. More specifically, at least the so-called point-to-point routing, from an input port to an output port, and the so-called point-to-multipoint routing, will be provided between an input port and several output ports. .

 We will find, in French patent applications Nos 8716475 and 8716476, the description of an elementary switch which may be suitable for producing such a switching network.

 This elementary switch receives cells on its inputs and selectively retransmits them on its outputs.

Two embodiments of the elementary switch are presented. The first of these forms, hereinafter referred to as direct routing, responds to the case where the received cells include, in a label, an indication of destination. In the elementary switch, by simple decoding, this destination indication provides the identity of at least one output to which the cell must be retransmitted, an identity which is then directly used to control the retransmission of this cell on each output thus designated. As the cell is intended to pass through other elementary switches, in a switching network, the destination indication comprises several parts which are used successively. The second of these forms, hereinafter referred to as translated routing, to which s' particularly addresses the present invention, responds to the case where the label contains a reference number called virtual circuit number. In each elementary switch, this reference number is used to address a translation memory which in return provides the identity of at least one output to which the cell must be retransmitted.

 It will be noted that, in these two forms of routing, the elementary switch itself does not intervene in the designation of the outputs to which the cell is retransmitted. In fact, an organ external to the switching network must supply the routing data identifying the path or paths of the cells in the switching network, that is to say either the destination indication contained in the label of the cells, for the first form of elementary switch considered, ie the data recorded in the translation memories of the elementary switches, with regard to the second form of elementary switches considered.

 The elementary switch with direct routing is particularly attractive, because of its simplicity it is enough to decode the indication of destination to deduce therefrom the designation of the output on which a cell must be retransmitted, in a point-to-point routing, or the designations of the outputs to which the cell must be retransmitted, in the case of point-to-multipoint routing. Its drawback is that it is no longer applicable in practice, as soon as the switching network has to broadcast a cell which reaches it on any input port, destined for any number of output ports. , provision should then be made that the broadcasting may have to take place in any elementary switch of the switching network; in this elementary switch, a received cell is retransmitted, identically, on several outputs. Several elementary switches of the next stage in the switching network will receive these identical cells. They will therefore not have the means to route the cell, each as far as it is concerned, to any specified output, designated by a specific destination indication on the cell label. This shows that this form of switch elementary is applicable, in a switching network with several stages of elementary switches, only in the last stage, and then only allows the diffusion on the outputs of a single elementary switch, which is not sufficient for the stated need.

 The basic switch with translated routing responds well to the need stated above in terms of broadcasting to any output ports, but has its own drawbacks. Indeed, the translation memory of each of the elementary switches must receive the output identities for each of the reference numbers capable of being routed by this elementary switch.

As the reference number must not include too many digits, for reasons of transmission efficiency, the number of reference numbers available is limited, and this means that they have to be reused, which leads to the need to provide each time new identities of outputs in the translation memories of the elementary switches, then to erase them later, and requires expensive means of transmission for this purpose. There are even configurations of switching networks in which the first stages carry traffic, so that a cell can be routed on any output of these first stages before being routed to its destination.

It is therefore concluded that the routing of any cell must be preceded by the provision of routing data to practically all the elementary switches of the switching network. This can be impractical when the number of elementary switches is high.

 The present invention aims to solve this last problem by proposing an elementary switch allowing the diffusion, but largely freed from the disadvantages previously mentioned as regards supply of routing information to the translation memories of the elementary switches, as well as a switching network of cells with asynchronous time multiplexing composed, at least in part, of such elementary switches and taking advantage of their advantageous characteristics.

The present invention therefore has as its first object an elementary switch for the switching of cells with asynchronous time multiplexing allowing broadcasting, comprising inputs, outputs, means of selective retransmission, to retransmit a cell, received on one of its inputs, on one or more of its outputs as a function of routing data associated with this cell, as well as retransmission control means determining the operating mode of said retransmission means. This elementary switch is characterized in that said retransmission control means include
- a translated routing device, to receive from the label of a cell received on one of the inputs a reference number and to translate it, using a translation memory, into one or more identities of output, each corresponding to at least one output, for the retransmission of the cell on an output for each output identity, designated from this identity,
a management unit arranged in particular to receive marking cells containing routing information received on the inputs of the elementary switch and to consequently record output identities in the translation memory,
non-selective routing means comprising in particular distribution routing means consisting in routing the received cell to all the outputs of the switch,
- routing mode selection means, provided for receiving from the label of a marking cell received on one of the inputs, routing mode data and for receiving a semi-permanent situation data from the switch elementary and provided for selectively controlling, as a function of these data, the implementation of the routing device, that of the non-selective routing means of distribution and / or the sending of this marking cell to said management unit.

 Thus, according to the situation of the elementary switch in the switching network, in the presence of a marking cell, the elementary switch routes the marking cell to a switch on the next stage, distributes it to all the switches of the stage according to which it has access, and / or transmits it to its own management unit.

 According to another characteristic of the invention, said routing mode selection means are also provided for receiving semi-permanent priority data from the elementary switch and for selectively controlling, as a function of this semi-permanent priority data and said routing mode data, the implementation or the inhibition of said distribution routing means.

 This also avoids unnecessary distributions.

 According to another characteristic of the invention, said non-selective routing means also comprise patching routing means arranged to route a received marking cell, on one of all the outputs of the elementary switch.

 According to another characteristic of the invention, said routing mode selection means are provided for receiving from the label of a marking cell received on one of the inputs, routing mode data which specifies a number of elementary switches in a switching network, and said routing mode selection means are arranged such that the routing device is implemented only when said floor number is equal or greater than a value derived from said semi-permanent situation data.

 A second object of the invention is a switching network comprising input ports, output ports, elementary switches arranged in several stages of interconnected elementary switches, each elementary switch having inputs and outputs and being arranged to transfer a cell received on one of its inputs, on one or more of its outputs, as a function of routing data associated with said cell, the network input ports corresponding to the inputs of the elementary switches of a first stage and the network output ports corresponding to the outputs of the elementary switches of a last stage. It is characterized in that the elementary switches of at least one of the stages of this switching network comply with the definition given above.

 According to another characteristic of the invention, the elementary switches of all the stages of this switching network are as defined above.

 According to another characteristic of the invention, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation data item is such that a patch routing mode is implemented in place of the translated routing mode, according to which any cell received is retransmitted on one of all the outputs of the elementary switch.

 According to another characteristic of the invention, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation data item is such that a patch routing mode is implemented in place of the translated routing mode, according to which any cell received is retransmitted on one of all the outputs of the elementary switch, chosen randomly or quasi-randomly.

 According to another characteristic of the invention, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent data is such that a patch routing mode is implemented in place of the d mode. translated routing, according to which any cell received is retransmitted on one of all the outputs of the elementary switch, chosen so as to equalize the traffic load of the cells on the outputs.

 According to another characteristic of the invention, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation datum is such as a distribution routing mode, causing the retransmission of a cell of marking received, on all the outputs of the elementary switch, is implemented for those of the marking cells intended for at least one first selective stage of the switching network.

 According to another characteristic of the invention, in certain elementary switches of at least one of the first stages of the switching network, said semi-permanent priority data is such that it inhibits the retransmission of a received marking cell, in order to avoid multiple retransmission of this cell by different paths to the same elementary switch of a next stage.

The various objects and characteristics of the invention will be explained in more detail in the course of the description which follows of an exemplary embodiment of the invention, provided without limitation, with reference to the appended figures which represent
FIG. 1, the known diagram of the circuits of an elementary switch in which the present invention is applied,
FIG. 2, the format of a cell label, provided for the implementation of the present invention,
FIG. 3, the diagram of output selection circuits according to the invention, applicable in the elementary switch of FIG. 1,
- Figure 4, a switching network according to the present invention.

 The diagram of Figure 1 is known. The invention applies, inter alia, to switches of this type. This elementary switch ensures the switching of cells with asynchronous time multiplexing between input links lel to lei and output links lsî to lsj.

 Each input link is provided with a reception circuit, CR1 to CRi, which detects the incoming cells, synchronizes them, and transmits them in a time slot assigned to the input link on an input bus BE. This bus can be a parallel bus, so that all the bits of a cell are accessible at the same time. The i slots of the input links follow each other in a recurring cycle of time division multiplexing of the input cells.

 A similar bus BS receives in a way that will be described later the cells to be transmitted in j successive time slots of a recurrent cycle of multiplexing of the output cells. Each of these slots is assigned to one of the output links lsî to lsj and supplies cells to one of the corresponding transmission circuits CTî to CTj. Each transmission circuit provides the interface between the transmission mode on the bus BS and the transmission mode on the links lsî to lsj.

 Each cell received and presented by the input bus BE is subjected to a buffer memory MT. If the received cell is to be retransmitted, it is saved in a location in the buffer memory designated by a write address AE supplied by a write address source SAE.

At the same time, the cell label, RT, is supplied to a DSS output selection device. If a routing mode data item contained in the RT label is such that the cell must be retransmitted, the device
DSS provides the write address source SAE with an rt signal which instructs it to prepare a new address for the next cell. Otherwise, the AE address is maintained and the next cell takes the place of the cell considered.

 In addition, the output selection device DSS, analyzing the RT label, in the manner which will be described later with reference to FIG. 3, marks on a control link AS the identity of any output on which the cell considered must be retransmitted. In practice, the control link AS can comprise j conductors, one per output link and the role of the DSS device is then to mark with a particular potential the conductor corresponding to any output to be thus selected.

Each of the conductors of the control link AS is connected to one of j queue memories fsl to fsj.

If this conductor is marked, it causes a registration operation by which address AE which is that of the location where the cell in question is recorded in the buffer memory MT, takes place in the queue. The queue memories are preferably of the first in / first out (FIFO) type. The FIFO memory fsl thus receives, as a function of the respective labels of the cells received, the addresses of the locations of the buffer memory MT containing the cells intended for the lsl link.

The same is true for the memory fsj, intended for the lsj link.

 On the occasion of each time slot on the output bus BS, the corresponding FIFO memory is read. It provides an AL read address. The corresponding location is read in memory MT and the cell read CLS is supplied on the output bus BS, to be transmitted on the corresponding output link.

 The cells received on the input links are thus temporarily recorded in the memory MT and, by time switching between the buses BE and BS can be transferred from any input link to any output link. The volume of the MT memory allows an unequal distribution of the bit rate between the output links, but the imbalance between the bit rates offered to the output links must not cause a congestion of one or more output links, such as the capacity of the MT memory or that of any of the queues is exceeded.

 Furthermore, the switching means which have just been described make it possible to retransmit a cell received and recorded in the buffer memory MT both on several output links and on a single one. It suffices to write the address AE of the location containing this cell in several FIFO memories instead of only one.

 To conclude, with regard to FIG. 1, mention will finally be made of the management unit UG connected to the buses BE and BS and thus capable of receiving certain cells, or of transmitting others. This management unit contains all the auxiliary circuits necessary to regulate the operation of the elementary switch, in particular a clock whose signals are distributed in order to control the operations in accordance with what has just been described.

 FIG. 2 represents a cell CEL comprising a label RT, followed by data DT. This RT label itself comprises three parts, an RCC command field, a destination indication in the form of an RCA network output address and an internal IRN reference number.

The RCC command field contains routing mode data which can designate a direct routing mode or a translated routing mode, or any other mode provided. If the RCC control field designates the direct routing mode, a destination indication taken from the RCA network exit address must be used to route the cell to an output making it possible to reach the indicated destination. If the control field
RCC designates the translated routing mode, the IRN reference number must be used for the routing of the cell on one or more corresponding outputs whose identities are available in the elementary switch as we will see a little later, by referring to figure 3.

 It will indeed be mentioned at this point that the RCA and IRN routing information are not always necessary both in the same cell and that, when only one of them is sufficient, which can be indicated by the RCC command field, the header will only include a routing information field, serving as appropriate for an RCA output address or an IRN internal reference number.

 FIG. 3 represents an embodiment of the output selection device DSS mentioned in FIG. 1 in which the present invention is applied.

 This device receives the RT label from a cell.

The control field RCC is applied to a control circuit CC which decodes it and combines it with a semi-permanent internal data item of situation SN and with a semi-permanent internal data item of priority SP, to supply the control signal sc of a multiplexer MTX control unit. This control circuit
CC also produces, for any cell which must be recorded in the buffer memory MT, the signal rt which commands the preparation of a new address of the buffer memory, with a view to recording the next cell. It also produces, for any service cell, which must be transmitted to the management unit UB, instead of the signals sc or rt, a service signal adl, which requests the management unit to read the cell then present on the entrance bus
BE.

The RCA network output address is transmitted to a cda address decoding device which also receives the semi-permanent data SN and provides in exchange one or more signals on the conductors of a direct control link AS1 connected to the multiplexer control
MTX. This cda device is thus a direct routing device which, receiving from the label of a cell received an indication of destination, translates it into an exit identity corresponding to at least one exit.

 The internal reference number IRN is applied, by the intermediary of a multiplexer of address mav to a translation memory MCV which provides in exchange one or more signals on the conductors of a translated control link AS2 also connected to the multiplexer MTX control unit. This translation memory is thus a translated routing device which, receiving from the label of a cell received a reference number, translates it into a donkey or several output identities.

 The MTX control multiplexer still receives signals on an AS3 patch control link and on an AS4 distribution link. On the AS3 patch control link, an output identity signal is present on one conductor only. The means used for this purpose are not indicated in the figure, but may include a shift register such that the output identity is sequentially changed at each cell, or else a selection circuit with quasi-random or pseudo-random operation. , or a selection circuit coupled to the FIFO memories of the outputs and such that the selected output identity is that of the least loaded output, etc.

The AS4 distribution link, for its part, carries a signal per conductor and causes the cell to be broadcast on all the outputs of the elementary switch. The MTX multiplexer selects the signals from one of the four control links AS1, AS2, AS3, AS4 and supplies them on the control link AS which is that of FIG. 1, determining the output links on which the cells are retransmitted. received and stored in the buffer of the basic switch.

 The address multiplexer mav, under the command of a registration address adg transmitted by the management unit UG, allows this management unit UG to introduce routing information into the translation memory mcv, by the mqv link.

 The means that we have just described thus allow four modes of routing: direct routing, translated routing, brewing routing and distribution, which will now be discussed, with reference to FIG. 4.

 FIG. 4 shows, by way of example, a configuration of a switching network according to the invention.

 The switching network shown is composed of selection units which include TSUi input terminal units, PS selection plans and TSUo output terminal units. In each selection unit, there are elementary switches which can be of the type of the preceding figures, each represented by the usual sign of a switching matrix, with, on the left, the number of the inputs of the elementary switch and, on the right, the number of its outputs. These elementary switches are interconnected by meshes.

 Inside an input terminal unit, TSUil for example, there are two stages of elementary switches, the elementary switches TSil to TSil6 and the elementary switches ASil to ASi4. There is a single mesh between an output of an elementary switch of the first stage and an input of an elementary switch of the second stage. The four outputs of a first stage switch, TSil for example, are each connected to an input of each of the four elementary switches of the second stage. Therefore, the 16 inputs of an elementary switch of the second stage, ASil for example, are each connected to an output of each of the 16 elementary switches of the first stage. The 64 inputs of the first stage elementary switches are connected to 64 pil input ports at pi64. The other input terminal units can be similar, except for the numerical values indicated. The output terminal units are arranged in the same way, but symmetrically. Thus the output terminal unit TSUol, for example, gives access, by the two stages of elementary switches comprising the elementary switches ASol to ASo4 and TSol to Sol6, to output ports pol to po64.

 The figure also shows TSUil28 and TSUo128 input and output terminal units, to indicate a total number of terminal units in the switching network.

The selection planes, such as the selection plan PS1, comprise three selection stages formed by the elementary switches PSil to PSi32, PScl to PSc16,
PSol to PSo32, which can be of the type which one has defined while referring to figures 1 and 3. The arrangement of the internal meshes between a stage and the following obeys the principle of that of the terminal selection units; we will not describe it in detail.

There are 16 selection plans PS1 to PS16. The 16 outputs of a switch of an input terminal selection unit, TSUil for example, are individually connected, by 16 meshes, to an input of each of the 16 selection planes. The 4 outputs of the same rank of the four elementary switches of a terminal input unit,
TSUil for example, are connected to successive inputs of the same elementary switch, PSil, for example of a selection plan, PS1 in this case. Therefore, the 512 inputs of a selection plan, PS1 for example, are connected, four by four, to the four elementary switches of each of the 128 input terminal units.

 The arrangement of the meshes between the outputs of the elementary switches of the third stage of the selection planes, PSol to PSo32 for the selection plane PS1 for example, and the inputs of the elementary switches of the second stage of the output terminal units is symmetrical with that we just described.

 The entire switching network is symmetrical with respect to the central stage of the selection planes. Each central elementary switch, such as PScl, accesses, by three switching stages, on each side, all the input ports and all the output ports. Conversely, between any input port and any output port, there are 256 separate paths, passing through the 256 central elementary switches. Taking into account that there is practically no internal loss, due to the use of the meshes between switches by means of a temporary recording in buffer memory allowing a relatively long wait, the routing of a cell can be done in a non-selective way between this input port and any of the switches central elementary. Then, the routing is necessarily selective, to reach the destination port of exit. If it is a question of reaching several distinct output ports, in a point-to-multipoint routing, this selective routing must include several branches.

 It will be noted that this network can comprise several links per mesh, each mesh then being connected from several outputs of an elementary switch of a stage to several inputs of an elementary switch of a following stage, the dimensions of the elementary switches being multiplied Consequently. This increases the traffic flow capacity of the switching network and, possibly, the number of input and output links that are connected to its ports. This would not change anything below, except for the numerical values mentioned and, in some cases, the need to make a selection between the different outputs relating to the same mesh, according to the methods already mentioned.

 Referring now to the foregoing descriptions, in particular relating to the retransmission control means illustrated by the output selection device of FIGS. 1 and 3, we will define how the different routing modes are applied in the elementary switches of the network. in Figure 4.

 We will first consider a direct route, for example between the pil input port and the pol output port.

In the cell label, a routing mode data item of the RCC control field specifies direct routing. The RCA output address comprises 7 bits designating the TSUol terminal unit and 6 bits designating the pol output port.

In the elementary switches of the first stage of the switching network, such as TSil, the semi-permanent data SN is such that, combined with the direct routing data, in the control circuit CC, it produces a value of the control signals sc such that the MTX multiplexer selects the AS3 control link. The cell is retransmitted on one of the set of all the outputs of the elementary switch. We have seen the conditions of this selection previously. For example, the cell is thus retransmitted towards the elementary switch
ASil.

 In the elementary switches of the second stage of the switching network, such as ASil, the semi-permanent data SN has the same effect as in the first stage and the cell is thus retransmitted on one of the set of all the outputs of the elementary switch, for example that which leads to the plane PS1 and, therein, towards the elementary switch PSil.

 The same applies in the elementary switches of the third stage of the switching network and the cell reaches for example the elementary switch PScî.

 From the central floor, the routing becomes selective, at least in part.

 The semi-permanent data SN of the switches of the central stage of the switching network is such that the control circuit CC, by the control signal sc, orients the multiplexer MTX on the control link AS1, while this same semi data -permanent SN, is applied to the decoding circuit cda, which also receives the output address RCA. In response, the cda circuit selects, from among the 7 bits which designate the destination terminal unit, the 5 bits which designate the single output leading to that of the 32 elementary switches of the fourth stage of the switching network which, in the plane PS1, accesses the destination terminal unit. Thus the output leading to the elementary switch PSol is selected.

 The operating mode is similar to that which we have just seen, in the elementary switches of the fifth stage of the switching network. The semipermanent data SN is different, but still causes the multiplexer MTX to be directed to the control link AS1. However, in the decoding circuit cda, this new value of the data SN causes the selection of the 2 remaining bits of the identity of the destination terminal unit, which identifies the four outputs leading to the four elementary switches ASol to ASo4 , according to the example considered. One of these four outputs is selected in the manner mentioned above (by sequential, quasi-random selection or as a function of the load, as already envisaged). It leads the cell, for example, to the ASol switch.

 In the elementary switches of the sixth stage of the switching network, the semi-permanent datum SN further directs the multiplexer MTX to the control link AS1, while the decoding circuit is this time put in a state such that it selects, from the 6 bits of the RCA address designating the output port, the 4 bits identifying the elementary switch serving this output port. The cell is thus led to the elementary switch TSol, in accordance with the example chosen.

 Finally, similarly, in the elementary switch of the last stage of the switching network, the semi-permanent indication SN causes the cell to be routed to the output port pol.

 During this direct routing, the semi-permanent indication SN therefore first made it possible to conduct the cell in a non-selective manner towards any elementary switch of the central stage, then to conduct it, selectively, in using successive parts of the RCA exit address, to the specified destination.

 It is easy to verify that, since all the elementary switches of the central stage, in a selection plane, see the 32 elementary switches of the fifth stage of this selection plane in the same way, the routing is identical in each of them. Likewise, since all the selection plans see the output terminal units in the same way, it can be concluded that all the basic switches of the central stage carry out the direct routing in the same way. A similar reasoning leads to the same conclusion with regard to the elementary switches of the other stages, from the fifth to the last. The conclusion is that the semi-permanent datum SN must in fact characterize only the identity of the stage in which the elementary switch is included, not its position in the stage.

 In addition, it should be emphasized that successive cells, from the same source and with the same destination can, mainly thanks to the routing routing practiced in the first stages of the switching network, take a large number of different paths, which achieves a mixing of traffic currents, favorable to the homogeneous flow of the rates of various cells subjected to the switching network.

 We will now treat, by comparison, the case of translated routing; the cell label contains in the RCC command field translated routing data, and also contains an internal IRN reference number. Initially, it will also be assumed, although this is not the preferred use of this routing mode, that it is a question of routing the cell to a single output port, again the port of pol output, for example.

 Despite a different routing data, the path from the cell in the non-selective part, to the central stage of the switching network, remains exactly that which has just been described and brings it, taking up the example considered, up to the elementary switch PScl.

In this one, the value of the semi-permanent datum SN is such that the control circuit CC, by the control signal sc, directs the multiplexer MTX towards the translated routing control link AS2. However, the internal reference number IRN, by the multiplexer mav oriented in an appropriate manner at that time, addresses the translation memory mcv, so that a corresponding location is read there. The routing information that sty is the identity of the fifth stage switch to be reached,
PSol in this case.

 Then, in the PSol switch, the process is strictly the same, and the information provided by the translation memory, read at the same address, is this time the identity of one of the outputs leading to one of the elementary switches of the sixth stage of the TSUo output terminal unit, ASol for example. As a variant, the identities of the four outputs leading to the four elementary switches ASol to ASo4 of this terminal unit could be obtained, but it would then be necessary to add to the device of FIG. 3 a free selection circuit as envisaged above (sequential, almost random, load sharing).

 The same goes for the next floors up to the last.

 The translated routing thus practiced thus offers exactly the same characteristics as the direct routing. In particular, it allows the stirring carried out in the first three stages of the switching network to be preserved, with the consequence that the cell path can pass through any of the elementary switches of the central stage of the network. However, it costs a marking operation consisting in registering in the translation memories of the elementary switches encountered on the various paths that the cell can take, routing information containing the appropriate identity or identities of outputs. We can easily see that the minimum is then to mark thus all the elementary switches of the central stage, then one per plan in the fifth stage, all the elementary switches of the sixth stage in the output terminal unit and, finally, the elementary switch of the last stage serving the target port of exit.

 However, the translated routing can, if desired, relate to a greater number of stages of the switching network, or even to all the stages of the network. It suffices to provide a particular routing data for this case, determining the application of the translated routing, for example from the first stage of the switching network. It is then possible to determine the end-to-end routing, by designating the output to be taken in each switch.

This can be used, in particular, in the context of maintenance operations. The marking operations to be planned will only concern one switch per floor.

 However, the advantage of the translated routing mode is essentially that it lends itself to point-to-multipoint routing, as already explained. We will therefore develop on this subject using the example of routing described above, with mixing to the central floor and selective routing only then.

For example, if the cell whose routing has just been described until the output port pol must also be retransmitted on other outputs of the elementary switch
TSol, it is sufficient that this is indicated in the translation memory, so that it provides, in exchange for the IRN reference number, routing information also designating these other outputs.

 If, in addition, this cell must also be retransmitted on one or more output ports served by other elementary switches of the last stage, but still in the same terminal unit TSU1, the routing information of the elementary switch ASol, or of each of the elementary switches ASol to ASo4 according to the variant envisaged above, must also be modified accordingly, while appropriate routing information must be written in the translation memories of the other elementary switches of the last stage.

 We are therefore in the process of broadcasting on any output ports of a terminal unit. Broadcasting on several output ports of several terminal units accessible by the same elementary switch on the fifth floor of each selection plane, requires marking accordingly in this switch on the fifth floor, in each selection plane, and the appropriate markings in the terminal units concerned, as we have just seen. In the case of terminal units depending on different switches on the fifth floor, it is also necessary, in each selection plane, to mark the switches on the central floor and these different switches on the fifth floor.

 By generalizing, broadcasting can involve a variable number of stages in the switching network, starting with the last. The fact of implementing the translated routing only from the central stage, already limits the recourse to the translated routing.

 In addition, the possibility of successively using direct routing and translated routing for the same cell allows additional limitation of the use of translated routing, as will now be seen.

 By first taking again the case of a diffusion on several output ports of the same elementary switch of the last stage, and by referring to the preceding descriptions, the direct routing will be practiced, using a label including routing data RCC interpreted, in the switches of the successive stages, as a function of the semi-permanent data SN of each of them, so as to cause a routing routing to the central stage, a direct routing, up to the sixth stage, directed by an output address RCA which can be the address of any output of the elementary switch considered, then the routing translated into this elementary switch only, directed by the reference number IRN. It can be seen that, in this case, the marking required may be only that of the switch concerned.

 If the broadcast involves output ports of several elementary switches of the same terminal unit, similarly, but with different routing data, direct routing will be used up to the fifth floor and the translated routing will concern the last two floors, in the terminal unit. The marking to be carried out will therefore be limited to the switches concerned in the terminal unit.

 If the diffusion is to extend in several terminal units accessible by the same elementary switch from the fifth stage, likewise, direct routing can be used for the fourth stage and the marking needs limited accordingly.

 All that is required is a set of similar routing data, different only in that they designate a different stage from which the translated routing mode is to be applied. It can also be said that the routing mode datum specifies a stage number of elementary switches and that the routing mode selection means are arranged so that the implementation of the translated routing mode does not take place only when the floor number is equal to or higher than that provided by the semi-permanent data SN.

 The requirements relating to the marking information which must be written in the translation memories of the switches are now defined. In the following, we will see how the present invention makes it possible to satisfy them in a particularly simple and effective manner.

 According to the invention, this marking information, transmitted in cells routed by the switching network, reaches the elementary switches of an entire switching stage by the use of the distribution routing mode, the use of internal data. priority SP allowing to get rid of superfluous distributions which would clutter the switching network unnecessarily.

 We will therefore first consider the marking of the elementary switches of the central stage, with a view to a translated routing aimed at output ports of the same terminal unit, TSU1 for example. Any input port of the switching network, pil for example, is used for the input of a marking cell whose tag includes a particular routing data.

The internal reference number and marking information containing the identification of the target terminal unit are included in the data section of the cell.

 In each crossed switch, the routing will take place, like the previous routing cases, by combination of the routing data and the semi-permanent situation data SN defining the stage in which the switch is located. In the TSil switch, this causes the cell to be distributed to all of the outputs. In the ASil switch, for example, the priority data SP being determined accordingly, this again causes the distribution of the cell to all the outputs, that is to say to an input of each selection plan. other switches of the same stage, ASi2 to ASi4, the priority data SP is different and inhibits the routing of the cell, which is obtained very simply in that - see FIG. 3 - the control circuit CC provides a control signal sc such that the MTX multiplexer does not select any control link.

 According to a variant, the information SP of the elementary switches ASil to ASi4, rather than inhibiting the routing of a cell already received in some of these elementary switches, could be carried over into the elementary switches of the previous stage, accessing to these switches ASil to ASi4, that is to say in the elementary switches Tsil to TsiT, so that the routing of a labeling cell by any one of these latter elementary switches, results in the selection of the priority elementary switch of the second stage, ASil in this case, which gives the same result as previously, with regard to the routing of the marking cell.

 Anyway, in the PSil switch of the PS1 plane, the same mechanism again causes the distribution of the cell on all the outputs. The cell thus reaches all the elementary switches of the central stage of selection plane PS1. The same goes for other plans. The marking cell, in each of these elementary switches, still due to its routing data, gives rise to the supply of the signal adl (FIG. 3) and to the reception of the cell by the management unit UG of the switch elementary (Figure 1). In return, the management unit sends output identity information to the translation memory mcv via the link mqv, the reference number IRN being supplied simultaneously on the address line adg and the multiplexer mav being at this time. oriented accordingly.

 The same method will be used to distribute a marking cell to elementary switches of the fifth stage. In each selection plan, all the elementary switches of the central stage receive this cell, but the only one in which the priority datum SP allows it will route the cell to all the switches of the following stage. These will accept the cell as a labeling cell. As the marking information contains a designation of the target terminal unit (TSUol) and due to the fact that a single elementary switch gives access to the selection unit TSUol, only this will take account of the marking received and will register in its translation memory corresponding output identity information.

 However, still according to the invention, provision will also be made to combine the two marking operations which have just been described. In fact, the content of the cell can be identical in both cases. The same cell is thus transmitted to the management units of the elementary switches of the central stage and is also retransmitted, by a priority elementary switch of each selection plan to the elementary switches of the following stage.

 The marking is identical if it is broadcasting to the output ports of several terminal units. It is enough that the cell identifies them all.

For this, the information conveyed by the marking cell can include, for example, one bit per terminal unit. If the cell is not large enough for this, several consecutive numbered cells can be used for this purpose. From this information, each switch on the central stage derives the corresponding output identities. The same goes for the interested switches of the next stage.

 A similar process will be applied for marking in the targeted terminal unit, TSUol. A marking cell containing the same reference number as in the previous case, but this time accompanied by the identification of the output port or ports to be marked is distributed to all the switches ASol to ASo4 of the penultimate stage of the 'terminal unit. One of them, priority, retransmits it to the switches of the top floor. Those only who give access to the targeted exit ports will take account of the marking received and will write, each in its translation memory, corresponding exit identity information.

Distribution to ASol to ASo4 elementary switches will be made from an elementary switch of a selection plan, determined for this purpose and reached by direct routing. To do this, the cell label includes a particular routing data, interpreted as direct routing data in the preceding stages of the switching network, accompanied by any indication of destination of the TSUol terminal unit. Arrival in the elementary switch in question,
PSol, for example, this particular routing data causes the distribution on the outputs leading to the TSUol terminal unit (instead of the selection of a single output).

 Of course, in the case of a broadcast targeting output ports of several terminal units, a marking must be carried out for each of them.

 It is thus seen, ultimately, that the invention makes it possible to reduce the tagging operations, in the event of dissemination, to a tagging of the selection plans, then to a tagging by targeted terminal unit, each tagging giving rise to the routing of 'a cell (or group of cells) up to the elementary switches concerned.

 It is obvious that the foregoing descriptions have been provided only by way of nonlimiting example and that numerous variants can be envisaged without thereby departing from the scope of the invention.

In particular, we have just described a network configuration in which the invention applies. There are many network configurations allowing patching operations in the first stages and selective operations in the following. And there are numerous configurations of selective stages comprising selection units which are accessed by central stages themselves arranged in selection units or other selection plans. It is obvious that the invention, with adaptations to the scope of the skilled person, would also find application.

Claims (11)

 1. Elementary switch for switching cells with asynchronous time division multiplexing allowing diffusion, comprising inputs, outputs, selective retransmission means, for retransmitting a cell, received on one of its inputs, on one or more of its outputs in routing data function associated with this cell, as well as retransmission control means determining the operating mode of said retransmission means, characterized in that said retransmission control means (DSS) comprise in particular  - a translated routing device (mcv), to receive from the label (RT) of a cell received on one of the inputs a reference number (IRN) and to translate it, using a translation memory (mcv), into one or more output identities (AS2), each corresponding to at least one output, with a view to retransmission of the cell on an output for each output identity, designated from this identity,  - a management unit (MU) arranged in particular to receive marking cells containing routing information received on the inputs of the elementary switch and to consequently record output identities in the translation memory (mcv),  - non-selective routing means (AS3, AS4) comprising in particular distribution routing means (AS4) consisting in routing the received cell to all the outputs of the switch,  - routing mode selection means (CC), designed to receive from the label (RT) of a marking cell received on one of the inputs (CR1, CRi) routing mode data ( RCC) and to receive a semi-permanent situation data (SN) from the elementary switch and provided for selectively controlling, as a function of these data, the implementation of the routing device (mcv), that of the routing means not selective distribution (AS4) and / or sending this marking cell to said management unit (UG).  2. Elementary switch for switching cells with asynchronous time division multiplexing according to claim 1, characterized in that, said routing mode selection means (CC) are also provided for receiving semi-permanent priority data (SP ) of the elementary switch and for selectively controlling, as a function of this semi-permanent priority datum and of said routing mode datum (RCC), the implementation or the inhibition of said distribution routing means (AS4) .  3. Elementary switch for switching cells with asynchronous time division multiplexing according to claim 1 or 2, characterized in that said non-selective routing means (SN, SP) also comprise arranged routing routing means (AS3) to route a received marking cell, on one of all the outputs of the elementary switch.  4. Elementary switch for switching cells with asynchronous time multiplexing according to claim 1, 2 or 3, characterized in that said routing mode selection means (CC) are provided for receiving the label (RT) of a marking cell received on one of the inputs a routing mode data item (RCC) which specifies a stage number of elementary switches in a switching network, and that said routing mode selection means are arranged so that the routing device is implemented only when said floor number is equal to or greater than a value derived from said semi-permanent situation data (SN).  5. Switching network comprising input ports, output ports, elementary switches arranged in several stages of interconnected elementary switches, each elementary switch having inputs and outputs and being arranged to transfer a received cell to one of its inputs, on one or more of its outputs, as a function of routing data associated with said cell, the input ports of the network corresponding to the inputs of the elementary switches of a first stage and the output ports of the corresponding network at the outputs of the elementary switches of a last stage, characterized in that the elementary switches of one of the stages (TSil, TSil6, etc.) at least of this switching network conform to any one of claims 1 to 4 .  6. Switching network according to claim 5, characterized in that the elementary switches of all the stages of this switching network conform to any one of claims 1 to 5.  7. Switching network according to claim 6, characterized in that, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation data (SN) is such that a mode d The routing routing is implemented in place of the translated routing mode, according to which any cell received is retransmitted on one of all the outputs of the elementary switch.  8. Switching network according to claim 6, characterized in that, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation data (SN) is such that a mode d 'routing routing is implemented in place of the translated routing mode, according to which any cell received is retransmitted on one of all the outputs of the elementary switch, chosen randomly or quasi-randomly.  9. Switching network according to claim 6, characterized in that, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation data (SN) is such that a mode d routing routing is implemented in place of the translated routing mode, according to which any cell received is retransmitted on one of all the outputs of the elementary switch, chosen so as to equalize the traffic load of the cells on the exits.  10. Switching network according to claim 6, characterized in that, in the elementary switches of at least one of the first stages of the switching network, said semi-permanent situation data (SN) is such that a mode d distribution routing, causing the retransmission of a received marking cell, on all the outputs of the elementary switch, is implemented for those of marking cells intended for at least one first selective stage (PScl, PSc16, etc.) of the switching network.  11. Switching network according to claim 10, characterized in that, in certain elementary switches of at least one of the first stages of the switching network, said semi-permanent priority data (SP) is such that it inhibits the retransmission of a received marking cell, in order to avoid multiple retransmission of this cell by different paths to the same elementary switch of a next stage.