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FR2368181A1 - CMOS logic resetting circuit - has different capacitances at two nodes to ensure circuit adopts correct logic states - Google Patents

CMOS logic resetting circuit - has different capacitances at two nodes to ensure circuit adopts correct logic states

Info

Publication number
FR2368181A1
FR2368181A1 FR7630560A FR7630560A FR2368181A1 FR 2368181 A1 FR2368181 A1 FR 2368181A1 FR 7630560 A FR7630560 A FR 7630560A FR 7630560 A FR7630560 A FR 7630560A FR 2368181 A1 FR2368181 A1 FR 2368181A1
Authority
FR
France
Prior art keywords
nodes
circuit
ensure
different capacitances
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7630560A
Other languages
French (fr)
Inventor
Jean-Pierre Michel Pillou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Laboratoire Central de Telecommunications SA
Original Assignee
Laboratoire Central de Telecommunications SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Laboratoire Central de Telecommunications SA filed Critical Laboratoire Central de Telecommunications SA
Priority to FR7630560A priority Critical patent/FR2368181A1/en
Publication of FR2368181A1 publication Critical patent/FR2368181A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails

Landscapes

  • Logic Circuits (AREA)

Abstract

The CMOS resetting circuit, for logic, consists of a bistable flip flop comprising two MOSFET inverters. The output of one inverter is connected to the input of the other. In order to ensure that node B has state '1' and node A state '0', the capacitance at node A is made greater than that of node B. This is achieved firstly by making the area of the gate of FET Q3 greater than that of Q4 and secondly by increasing the diffusion area at A (i.e. the diffusion area of Q2's source and Q4's drain) so that it is greater than that associated with B (i.e. the diffusion area of Q1's source and Q3's drain).
FR7630560A 1976-10-12 1976-10-12 CMOS logic resetting circuit - has different capacitances at two nodes to ensure circuit adopts correct logic states Withdrawn FR2368181A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7630560A FR2368181A1 (en) 1976-10-12 1976-10-12 CMOS logic resetting circuit - has different capacitances at two nodes to ensure circuit adopts correct logic states

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7630560A FR2368181A1 (en) 1976-10-12 1976-10-12 CMOS logic resetting circuit - has different capacitances at two nodes to ensure circuit adopts correct logic states

Publications (1)

Publication Number Publication Date
FR2368181A1 true FR2368181A1 (en) 1978-05-12

Family

ID=9178614

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7630560A Withdrawn FR2368181A1 (en) 1976-10-12 1976-10-12 CMOS logic resetting circuit - has different capacitances at two nodes to ensure circuit adopts correct logic states

Country Status (1)

Country Link
FR (1) FR2368181A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2398402A1 (en) * 1977-07-22 1979-02-16 Siemens Ag CIRCUIT FOR THE PRODUCTION OF A POSITIONING PULSE OF THE ELECTRONIC CIRCUIT OF AN ELECTRONIC DEVICE, IN PARTICULAR OF AN ELECTRONIC DEVICE AT MAXIMUM
FR2439508A1 (en) * 1978-10-18 1980-05-16 Siemens Ag SEMICONDUCTOR DIGITAL INTEGRATED CIRCUIT

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2083657A1 (en) * 1970-03-30 1971-12-17 Ibm
US3753011A (en) * 1972-03-13 1973-08-14 Intel Corp Power supply settable bi-stable circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2083657A1 (en) * 1970-03-30 1971-12-17 Ibm
US3753011A (en) * 1972-03-13 1973-08-14 Intel Corp Power supply settable bi-stable circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NV202/73 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2398402A1 (en) * 1977-07-22 1979-02-16 Siemens Ag CIRCUIT FOR THE PRODUCTION OF A POSITIONING PULSE OF THE ELECTRONIC CIRCUIT OF AN ELECTRONIC DEVICE, IN PARTICULAR OF AN ELECTRONIC DEVICE AT MAXIMUM
FR2439508A1 (en) * 1978-10-18 1980-05-16 Siemens Ag SEMICONDUCTOR DIGITAL INTEGRATED CIRCUIT

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Legal Events

Date Code Title Description
ST Notification of lapse