FI914733L - TEST METHOD AND TEST APPARATUS - Google Patents
TEST METHOD AND TEST APPARATUS Download PDFInfo
- Publication number
- FI914733L FI914733L FI914733A FI914733A FI914733L FI 914733 L FI914733 L FI 914733L FI 914733 A FI914733 A FI 914733A FI 914733 A FI914733 A FI 914733A FI 914733 L FI914733 L FI 914733L
- Authority
- FI
- Finland
- Prior art keywords
- test
- arrangement
- standardized
- area
- structures
- Prior art date
Links
- 238000010998 test method Methods 0.000 title abstract 2
- 238000003745 diagnosis Methods 0.000 abstract 2
- 238000005259 measurement Methods 0.000 abstract 2
- 230000007547 defect Effects 0.000 abstract 1
- 238000001514 detection method Methods 0.000 abstract 1
- 230000004807 localization Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention concerns a test method and test apparatus for detection and localization of manufacturing defects in an electronic arrangement that contains test structures according to standard IEEE 1149.1, hereafter "the tested arrangement" by means of selected current diagnosis. The selected current diagnosis significantly broadens the area of application of wiring tests according to standard IEEE 1149.1 (JTAG) on component boards that contain both components with standardized test structures and traditional components without the standardized test structure. Broadening of the area of application and the increased coverage of wiring tests are based on measurement of changes in the value of the operating current that an arrangement takes from a power source by means of a computer-control test arrangement that contains a current measurement device and a control device for the test structures, when the test arrangement by means of the standardized test structure placed in the test arrangement has guided the test arrangement into a desired controlled static state or states. <IMAGE>
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FI914733A FI100829B (en) | 1991-10-08 | 1991-10-08 | Test method and test apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FI914733A FI100829B (en) | 1991-10-08 | 1991-10-08 | Test method and test apparatus |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| FI914733A0 FI914733A0 (en) | 1991-10-08 |
| FI914733L true FI914733L (en) | 1993-04-09 |
| FI100829B FI100829B (en) | 1998-02-27 |
Family
ID=8533253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FI914733A FI100829B (en) | 1991-10-08 | 1991-10-08 | Test method and test apparatus |
Country Status (1)
| Country | Link |
|---|---|
| FI (1) | FI100829B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FI110034B (en) * | 2000-02-11 | 2002-11-15 | Elektrobit Oy | Test arrangement and test procedure |
| US7206547B2 (en) | 2003-09-30 | 2007-04-17 | Elektrobit Oy | Method of testing electric circuit, and arrangement |
-
1991
- 1991-10-08 FI FI914733A patent/FI100829B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| FI914733A0 (en) | 1991-10-08 |
| FI100829B (en) | 1998-02-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PC | Transfer of assignment of patent |
Owner name: ELEKTROBIT TESTING OY Free format text: ELEKTROBIT TESTING OY |
|
| PC | Transfer of assignment of patent |
Owner name: ELEKTROBIT SYSTEM TEST OY Free format text: ELEKTROBIT SYSTEM TEST OY |