FI20185058A1

FI20185058A1 - Packaged microelectronic component and method of manufacturing thereof

Info

Publication number: FI20185058A1
Application number: FI20185058A
Authority: FI
Inventors: Heikki Viljanen; Antti Jaakkola
Original assignee: Tikitin Oy
Priority date: 2018-01-22
Filing date: 2018-01-22
Publication date: 2019-07-23
Also published as: WO2019141908A1

Abstract

The invention relates to a microelectromechanical component and method of manufacturing thereof. The component comprised a semiconductor body comprising a device layer, a microelectronic element utilizing the device layer, and a cap layer bonded to the semiconductor body along a bonding zone so as to form a hermetically isolated space containing the microelectronic element therein. In addition, there is provided at least one electric pathway between the interior and exterior of the isolated space so that the electric pathway is formed of a patterned section of the device layer electrically isolated from the rest of the device layer and doped so as to increase its electrical conductivity. The invention simplifies packaging of for example MEMS components, such as resonators.

Description

Packaged microelectronic component and method of manufacturing thereof

Field of the Invention

The invention relates to microelectronic components, for example micromechanical components, such as resonators. In particular, the invention relates to wafer-level5 packaged (WLP) microelectromechanical resonators in which the resonator operates in hermetically sealed space in a vacuum. The invention also relates to a method of manufacturing such components.

Background of the Invention

Wafer-level packaging is necessary in the production-scale manufacturing of high10 performance microelectromechanical (MEMS) resonators. The aim is to produce as small as possible sealed space around a micromechanical resonator element, that protects the resonator element physically and is capable of maintaining a vacuum around the resonator in order to ensure its undisturbed oscillation. A common solution is to bond a cap to the wafer using a sealing ring or the like. Further, electrical wiring must be arranged between the exterior and interior of the sealed space for any electric components that reside inside the space, most notable the required transducer, i.e. excitation and/or sensing mechanism, of the resonator element. Providing the electric wiring poses problems for the packaging phase, in which the complexity and costs should be minimized.

In some existing solutions, the cap of the package is provided with vertical through-silicon vias that at filled with conductive material and bonded inside the sealed space to necessary components therein. This adds complexity and costs to the capping phase since additional steps are required to manufacture the vias and bonds.

In some existing solutions, the through-silicon vias are arranged to the sealed space from below, i.e. through the wafer which contains the MEMS component. This is, however, generally not desired because it necessitates two-sided processing of the wafer.

Through-silicon vias are discussed e.g. in US 2013/0001710 A1.

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US 2016/0221824 discloses an alternative solution comprising a profiled glass substrate and a MEMS component positioned on the glass substrate. A metal wire is produced on the glass substrate and connected to the MEMS component. A capping wafer is provided on the glass substrate to define a sealed space entirely containing the metal wire and a vertical via is manufactured into the capping wafer inside the region of the sealed space to the metal wires in order to make electrical contact with the MEMS component. In one variation, the glass substrate is replaced with a silicon wafer containing a silicon lead, which is used instead of the metal wire to make the contact between the vertical via of the capping wafer and the MEMS component inside the sealed space. This technique requires two wafers and also vertical processing of the capping wafer, which add costs and complexity of the process. Another variation of this technology, eliminating the need of the second SOI wafer but still requiring vertical vias inside the sealing region and additionally metal routing on a glass cap layer, is discussed in Torunbalci M. M. et al A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process, J. Micromech. Microeng. 25 (2015) 125030 (11pp) doi:10.1088/0960-1317/25/12/125030.

US 7312505 discloses a solution in which an “external interconnection” is provided in the form of a conductive trace or well produced directly on a silicon substrate, onto which the cap is bond. US 7531424 discusses a solution in which first a dielectric layer is provided 20 on the device layer of the wafer and then conductive metallic interconnection lines are manufactured on dielectric layer. The cap is bonded to the metallic interconnect lines on regions where the sealing ring of the cap crosses them. Also this method requires many production steps and layers for achieving the interconnections, and makes difficult to ensure the tightness of the sealed space due to the layers.

Thus, there is a need for improved techniques for producing the electrical connections between the sealed space and its surroundings.

Summary of the Invention

It is an aim of the invention to overcome at least some of the abovementioned drawbacks.

In particular, it is an aim to provide a simpler electrical connection scheme of microelectronic devices, such as MEMS devices, in particular resonators. A specific aim is to provide a simplified and reliable connection scheme usable for wafer-level packaging of temperature-compensated MEMS resonators.

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The invention is based on using of a doped silicon layer of a packaged microelectronic component as a signal pathway between the interior and exterior of the package. In more detail, in the present invention, a device layer that is made of semiconductor material is patterned to form an electric pathway that is electrically isolated from the rest of the device 5 layer so that the pathway crosses the boundary of the package of the component. The electric conductivity of the pathway is achieved by a doping agent provided within the silicon in sufficient amount, typically to a degenerate doping level. These device layer vias simplify the structure and manufacturing process of the component. A microelectronic element within the package can also be at least partially doped to alter its 10 electric and/or micromechanical behavior. In the case of MEMS elements, the doping can be carried out in particular for temperature compensation purposes. In some cases, the whole device layer is doped.

In particular, the invention is characterized by what is stated in the independent claims.

According to one aspect, the invention provides microelectronic component, such as a 15 microelectromechanical (briefly micromechanical) element comprising a semiconductor body having a device layer, and a microelectronic element which utilizes the device layer. For example, a micromechanical element can be patterned directly into the device layer.

In addition, there is a cap layer bonded to the semiconductor body along a bonding zone so as to form a hermetically isolated space containing the microelectronic element therein, 20 and at least one electric pathway between the isolated space and its surroundings.

According to the invention, the electric pathway is formed of a patterned and doped section of the device layer electrically isolated from the rest of the device layer. In particular, both the microelectronic element that forms the core of the component, or part thereof, and its signal path, or some other electrical pathway relating to the operation of 25 the element, can be patterned into the very same at least partially doped semiconductor layer of the semiconductor body.

According to another aspect, there is provided a method of manufacturing a microelectronic component, the method comprising providing a silicon-on-insulator wafer comprising a device layer, which is at least partly doped to increase its conductivity. The 30 device layer is processed to provide a microelectronic element which at least partly takes advantage of the device layer, and a trench which defines an electric pathway directed at least partly away from the micromechanical element. The trench is filled at least partially with electrically insulating material and a cap is bonded onto the wafer along a bonding

20185058 prh 22 -01- 2018 zone in order to provide a hermetically sealed zone around the micromechanical element such that the bonding zone intersects with the trench and the electric pathway.

The invention also provides a novel use for a doped device layer of a MEMS component for forming wafer level package boundary -crossing vias.

The invention offers significant benefits. First, with the device layer vias, there is no need for through-silicon vertical vias, which simplifies the manufacturing process. In addition to that, there is no need for additional horizontal conductive material layers at the bonding zone on top of the device layer or embedded therein, which would complicate the capbonding and increase contact resistance of the pathway. There is also no need for contacts between the cap wafer and the base wafer of the component. Consequently, many existing cap and sealing ring combinations and their application methods can be used in connection with the invention.

The bonding accuracy of the cap is also relieved for example compared with methods requiring through vias.

The invention allows for manufacturing all electrical contacts to the electric pathway both inside and outside the sealed space to be made from the device layer side. Thus, the handle layer of the SOI wafer typically used as the semiconductor body need not be processed in any way for contacting purposes. Thus, the component can be free from vertical vias extending through the semiconductor body or through the cap layer at least at 20 the region of the hermetically isolated space, preferably entirely.

The invention provides particular advantages in the case of temperature-compensated micromechanical elements, i.e. elements that have optimized dependency on temperature, and which utilize material properties of the micromechanical element to achieve this. In many cases doping of silicon to a certain level makes the behavior of the 25 element insensitive or less sensitive to temperature changes compared with non-doped silicon. Of particular importance herein are resonators, whose output frequency needs to be stabilized.

Thus, in one particular embodiment, the micromechanical element is a resonator element shaped and oriented with respect to the crystal direction of the device layer such that in 30 combination with the doping, the temperature coefficient of frequency of the resonator element in at least one resonance mode is smaller than without said doping.

The signal pathway may act as an excitation and/or sensing signal pathway of the resonator. In this case, the resonator element may comprise for example a piezotransducer or electrostatic transducer inside the isolated space for exciting the resonator element into a resonance mode, the electric pathway being electrically connected to the transducer inside the isolated space.

The invention can be used in wafer-level packaging of various types of devices. In addition to MEMS resonators, the invention can be used in connection with other types of MEMS devices, such as mechanical sensors, in particular if it is beneficial to use degenerately doped device layer for temperature-compensation purposes or other purposes. The invention can also be used in other types of microelectronic components than MEMS components that require hermetic sealing of the core of the component.

In some embodiments, the patterned section of the device layer forming the electric pathway and at least part of the microelectronic element are doped, typically to the same doping concentration, and optionally with the same doping profile in the depth direction. In 15 a specific example, the electric pathway is homogeneously doped. In a further example, the micromechanical element is homogeneously doped. In still another example, the whole device layer (and therefore also all portions of the component manufactured by patterning the device layer) is homogeneously doped.

The dependent claims are directed to selected embodiments of the invention.

Next, selected embodiments of the invention and advantages thereof are discussed in more detail with reference to the attached drawings.

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Brief Description of the Drawings

Fig. 1 shows a cross-sectional side view of the present component according to one embodiment.

Fig. 2 shows a top view of the present component according to one embodiment.

Figs. 3A-K illustrate as cross-sectional side views steps of an exemplary microfabrication method for the present structure.

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Detailed Description of Embodiments

Definitions

Degenerate doping herein means doping of semiconductor crystal with a doping agent and concentration suitable to give the crystal metallic or close to metallic conductivity. In particular, the doping concentration can be 2*10¹⁹ cm'³or more, such as 10²° cm’³ or more. With such doping levels, not only the electrical conductivity, but also elastic properties of the crystal are different from a pure silicon crystal. The doping agent may be either an n- or p-type doping agent, such as phosphorus or boron.

Microelectronic element generally covers microelectromechanical elements, such as micromechanical resonators and sensors, and non-micromechanical elements, such as transistors, capacitors, inductors, resistors, diodes, sensors and integrated circuits. Depending on the type of the element, it may be fabricated by patterning the device layer and/or providing one or more additional layers onto the device layer, and/or utilizing the device layer in some other way to provide a functional core for the component. In one embodiment, the element is partly or entirely fabricated in-situ into or onto the device layer by microfabrication techniques, thus excluding separate components manufactured elsewhere and simply bonded to the device layer.

Resonator element may be a surface acoustic wave resonator or, and in particular, a bulk acoustic wave (BAW) resonator. The resonator may be adapted to resonate in any in-plane and out-of-plane resonance mode characteristic to its shape. Examples include extensional modes, flexural modes, and torsional modes. Typical shapes include rectangular plate shapes, such as square plate shape, and beam shapes. The resonator may also be a resonator array or many-element coupled resonator.

Temperature-compensated element herein means that the elastic properties of the element that are relevant for the mechanical movement the element is adapted to undergo have, with the present doping level used, smaller dependency on temperature than without such doping in at least some temperature range. Typically, temperature compensation is a result of selection of material properties, geometric properties, crystalorientation -related properties and mode shape of the resonator. Temperature compensation herein covers also so-called overcompensation, i.e. making the TCF of the element as such positive so that when a piezoelectric transducer layer, and/or some

20185058 prh 22 -01- 2018 other layers are, coupled with the element, the total TCF of the resonator is smaller than without doping.

Description of selected embodiments

Figs. 1 and 2 illustrate one possible component design taking advantage of the present invention. The component comprises a common silicon-on-insulator (SOI) structure having a silicon base layer 102 and a device layer 104 separated by a and a dielectric separation layer 103. The device layer 104 is degenerately doped.

The core of the component is the micromechanical element 110 patterned into the device layer 104 and suitably separated from the base layer 102. In this exemplary case, the micromechanical element 110 is a cantilever-type resonator. At another region of the device layer 104, there is the electric pathway 120 also patterned to the device layer 104. The electric pathway 120 is separated from the rest of the device layer 104 by a trench 121 which extend from the upper surface device layer 104 to the dielectric layer 103. The trench 121 is filled with insulating material up to the device layer 104 surface level.

As shown in Fig. 2, the trench 121 (here three separate trenches 121A-C) intersects with the bonding zone, therefore defining a separated section of the device layer 104 across the bonding zone. The separated section forms the electric pathway 120.

On top of the device layer 104, there is provided a cap 107, typically also made of silicon, which is sealed against the device layer 104 using a sealing ring 106 that forms a loop around the micromechanical element 110, and therefore closes together with the cap 107 a hermetically sealed space 109 where the micromechanical element 110 resides. The cap may also be a glass cap, for example.

Although it is preferred to fill the trench 121 entirely with insulating material, in some embodiments only a smaller section of the trench 121 is filled, the section however covering the region of the sealing ring 106 to ensure tightness.

In some embodiment, the trench first overfilled and then the filling material is planarized to the surface level of the device layer 104.

In some embodiments, there is provided an additional dielectric layer (not shown) between the device layer 104, including the pathway 120 therein, and the sealing ring

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106, at the bonding zone so ensure adhesion and/or tightness of the seam or to decrease coupling of the device layer 104 and the pathway 120 from the seal layer 106 and cap

107. While a single-material sealing is possible if the material of the sealing ring is dielectric, the two (or more) material solution allows for using conductive sealing ring materials.

The invented packaging process is compatible with all of the standard wafer level encapsulation processes and their deviants such as metallic bonding, anodic bonding and glass frit bonding. A specific example is eutectic Au-Si bonding.

In some cases, a single electric pathway may be sufficient, but in typical cases there are at least two, such as 2 -10 electric pathways patterned into the device layer. The pathways may be arranged on different sides of the element. However, by arranging the all pathways on a single side, the footprint of the component can be minimized. What is said herein in the context of the structure and in particular the pathway 120 shown in Fig.

1, applies to all pathways in the case of multiple pathways, i.e. in a device layer multi-via 15 configuration.

Fig. 2 shows an example with three electric pathways 120A, 120B, 120C. Each of the pathways is herein formed by a separate trench 121 A, 121B, 121C, although a single trench surrounding each of the pathways 120A, 120B, 120C could in principle be used too.

The pathways 120A, 120B, 120C in this example have a bone- or dumbbell-shape, with their ends (terminal zones serving as contact pads) being larger in cross-section than the central (wire) portion. The pathways may, however, take any other shape that extends from the outside of the isolated space 109 to the inside thereof. Two of the pathways 120A, 120B, are in this example connected using conductive wires 112A, 112B to functional areas of the micromechanical element 110.

Fig. 2 also illustrates a preferred configuration, in which the outer terminal ends of the pathways 120A, 120B, 120C are located on the same side of the component in the lateral direction. This allows for minimizing the footprint of the component.

As discussed above briefly, in some embodiments the micromechanical element is a resonator element, in particular a temperature-compensated resonator element, which is at least partially temperature-compensated by taking advantage of the degenerate doping of the device layer. Referring back to Fig. 1, on top of the resonator element 110, there

20185058 prh 22 -01- 2018 may be provided a piezoelectric layer 111 and an electrode layer 112A, forming a transducer for the resonator. The electrode layer is connected to internal end of the electric pathway using a conductor wire 112B, separated from the device layer 104 using an insulation layer 113. The conductor wire 112B, and typically also the insulation layer

113 cross the trench 121 inside the isolated space 119. Thus, a complete electrically conductive path is formed from the outside of the isolated space 109 up to the electrode 112A of the transducer.

More generally, in some embodiments, the interior end of the pathway and the micromechanical element are electrically connected by there is provided a passivation 10 layer on top of the device layer inside the hermetically isolated space, the passivation layer extending at least partially on top of the electrically insulating material in the trench. Conductive wiring is arranged between the pathway and the element also entirely inside the hermetically isolated space and partially located on the passivation layer. The wiring therefore forms a conductive bridge over the trench without short-circuiting the pathway 15 with the rest of the device layer.

The electrode 112A and conductive wire 112B may in practice be formed of a unitary structure of the same material, typically a metal.

Electric contacting to the pathway 120 at the exterior side of the sealed space 109 can be made with metal wiring on the surface of the device layer 104, separated therefrom with a 20 dielectric layer outside the trench 120, or using other known bonding techniques such as wire bonding. Notable is, that since the pathway extends outside the hermetic package, these contacts can be made completely outside the region of the sealed space and without risk of losing the hermeticity of the component.

The isolated space is preferably vacuumized in the fabrication phase.

Next, an exemplary fabrication method is briefly described with reference to Figs. 3A-K.

Fig. 3A shows a SOI wafer after doping of the device layer and forming a cavity for the resonator element in a cavity-SOI (CSOI) process. In the step of Fig. 3B, one or more isolation trenches are etched to the device layer to define the device layer via(s). In the step of Fig. 3C, the isolation trench is overfilled with dielectric material, e.g. tetraethyl orthosilicate (TEOS process) or a combination of e.g. PECVD silicon nitride and polysilicon. In the step of Fig. 3D, the dielectric layer is patterned to provide passivation layers at the cap bonding zone, and optionally other regions, such as the signal line routes

20185058 prh 22 -01- 2018 outside the cap bonding zone. In some embodiments, the dielectric layer, apart from the trench fills, is entirely removed with e.g. a chemical-mechanical planarization (CMP) process. In the step of Fig. 3E, a piezoelectric transducer is produced on the resonator element with an AIN layer, a separation layer and a molybdenum electrode in contact with the AIN layer and wired to the inner terminal of the device layer via. A PECVD process can be employed. In the step of Fig. 3F, a stepper patterned hard mask for resonator portion release etch is produced. In the step of Fig. 3G, a seal layer, for example a gold layer, is deposited and patterned on the cap bonding zone (sealing ring) onto the passivation layer and optionally other regions as required, such onto the outer terminal of the device layer via. As discussed above, in case a dielectric sealing ring is used, the passivation layer at the bonding zone can be omitted. In the step of Fig. 3H, the resonator portion is released in a lithographic etch process. In the step of Fig. 3I a cap is provided on the wafer, supported by the sealing ring. A cavity may be provided at the region of the outer terminal to ensure tight contact. In the step of Fig. 3J, the cap is diced. In the step of

Fig. 3K, the MEMS component is singulated. The resulting structure corresponds to that discussed above with respect to Figs. 1 and 2.

Variations to the method described above, including other suitable processes for manufacturing the trenches, bonds and material layers herein discussed, as well as suitable dielectric and conductive materials therefor, are widely known in the art and available for a skilled person and therefore not discussed herein extensively.

Although piezoelectric transduction is herein discussed in detail, the present device layer vias are suited for electrostatic transduction as well. In one example, a surface of the electric pathway, or a conductive coating arranged thereon, inside the sealed space operates as a transducer electrode facing the micromechanical element over a gap.

Citations list

Patent literature

US 2013/0001710 A1

US 7312505

US 7531424

US 2016/0221824

Non-patent literature

Torunbalci M. et al A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process, J. Micromech. Microeng. 25 (2015) 125030 (11pp) doi:10.1088/0960-1317/25/12/125030.

Claims

Claims

1. A microelectronic component comprising

- a semiconductor body comprising a device layer,

- a microelectronic element utilizing the device layer,

5 - a cap layer bonded to the semiconductor body along a bonding zone so as to form a hermetically isolated space containing the microelectronic element therein,

- at least one electric pathway between the interior and exterior of the isolated space, wherein

10 - the electric pathway is formed of a patterned section of the device layer electrically isolated from the rest of the device layer and doped so as to increase its electrical conductivity.
2. The component according to claim 1, wherein both the the patterned section of the device layer forming the electric pathway and at least part of the microelectronic element

15 are doped.
3. The component according to claim 1 or 2, wherein the patterned section of the device layer forming the electric pathway, typically the whole device layer, is essentially homogeneously doped.
4. The component according to any of the preceding claims, wherein the electric pathway

20 is defined by a trench provided in the device layer, the trench intersecting with the bonding zone so as to define the electric pathway across the bonding zone, and the trench being filled with electrically insulating material at least at the region of the bonding zone, preferably entirely.
5. The component according to claim 4, comprising

25 - a passivation layer on top of the device layer inside the hermetically isolated space and extending at least partially on top of the electrically insulating material in the trench

- conductive wiring inside the hermetically isolated space and partially located on the passivation layer, the wiring bridging the trench so as to electrically connect

30 the interior end of the pathway and the microelectronic element.

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6. The component according to any of the preceding claims, wherein the cap layer is hermetically bonded to the device layer or to a passivation layer provided thereon using a sealing ring made of dielectric and/or metallic material.
7. The component according to any of the preceding claims, wherein the semiconductor

5 body is a silicon-on-insulator wafer comprising a handle layer and said device layer, and wherein all electrical contacts to the electric pathway both inside and outside said sealed space are made from the device layer side.
8. The component according to any of the preceding claims, wherein the microelectronic element is a microelectromechanical element fabricated into the device layer.
10 9. The component according to claim 8, wherein the microelectromechanical element is a resonator element.

10. The component according to claim 9, wherein the resonator element is also formed of a doped section of the device layer and at least partially temperature-compensated by taking advantage of the doping of the device layer.

15
11. The component according to claim 9 or 10, comprising an electric transducer inside the isolated space for exciting the resonator element into a resonance mode, and wherein the electric pathway is electrically connected to the transducer inside the isolated space.
12. The component according to any of the preceding claims, wherein the component is free from vertical vias extending through the semiconductor body or through the cap layer

20 at least at the region of the hermetically isolated space, preferably entirely.
13. The component according to any of the preceding claims, wherein the electric pathway is shaped to contain terminal zones on both ends thereof, and a connection line between the terminal zones, the connection line having a cross sectional area smaller than that of the terminal zones.

25
14. The component according to any of the preceding claims, comprising at least two such electric pathways patterned into the device layer.
15. The component according to claim 14, wherein the at least two electric pathways comprise external terminals, which are located on the same side of the microelectronic component in the lateral direction.

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16. The component according to any of the preceding claims, wherein the device layer is doped to a doping concentration of 2*10¹⁹ cm'³or more, in particular 10²° cm'³ or more, at least at the region of the electric pathway.
17. The component according to any of the preceding claims, wherein the electric

5 pathway is functionally connected to the micromechanical component or to a heater or temperature sensing element of the micromechanical component placed inside the isolated space.
18. A method of manufacturing a microelectronic component, such as a microelectromechanical resonator component, the method comprising

10 - providing a silicon-on-insulator wafer comprising a device layer,

- processing the wafer to provide a microelectronic element, such as a microelectromechanical resonator element, utilizing the device layer,

- manufacturing a trench in device layer in order to define an electric pathway directed at least partly away from the microelectronic element, the device layer

15 being doped using a doping agent at least at the region of the electric pathway,

- filling the trench at least partially with electrically insulating material, and

- bonding a cap onto the wafer along a bonding zone in order to provide a hermetically isolated space around the microelectronic element such that the bonding zone intersects with the trench and the electric pathway.
20 19. The method according to claim 18, wherein

- the microelectronic element is a microelectromechanical resonator element fabricated into the device layer,

- the device layer is doped also at the region of the resonator element, and

- the method comprises shaping and orienting the resonator element with respect to
25 a crystal direction of the device layer such that in combination with the doping, the temperature coefficient of frequency of the resonator element in at least one resonance mode is smaller than without said doping.

20. The method according to claims 18 or 19, wherein a component according to any of claims 1 - 17 is manufactured.
30 21. Use of at least partially doped silicon layer of a packaged microelectronic component as a signal pathway between the interior and exterior of the package.