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FI20040418A7 - Digitaalijärjestelmän kellokontrolli - Google Patents

Digitaalijärjestelmän kellokontrolli Download PDF

Info

Publication number
FI20040418A7
FI20040418A7 FI20040418A FI20040418A FI20040418A7 FI 20040418 A7 FI20040418 A7 FI 20040418A7 FI 20040418 A FI20040418 A FI 20040418A FI 20040418 A FI20040418 A FI 20040418A FI 20040418 A7 FI20040418 A7 FI 20040418A7
Authority
FI
Finland
Prior art keywords
system clock
clock signal
digital system
clock control
detect
Prior art date
Application number
FI20040418A
Other languages
English (en)
Swedish (sv)
Other versions
FI20040418L (fi
FI20040418A0 (fi
Inventor
Erkki Nokkonen
Original Assignee
Nokia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp filed Critical Nokia Corp
Priority to FI20040418A priority Critical patent/FI20040418L/fi
Publication of FI20040418A0 publication Critical patent/FI20040418A0/fi
Priority to US11/059,741 priority patent/US20050210301A1/en
Priority to EP05717337A priority patent/EP1738241A1/en
Priority to PCT/FI2005/050084 priority patent/WO2005088423A1/en
Publication of FI20040418A7 publication Critical patent/FI20040418A7/fi
Publication of FI20040418L publication Critical patent/FI20040418L/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Electric Clocks (AREA)

Abstract

Digitaalijärjestelmä,järjestelmän implementoima menetelmä ja kannettava laite, johon järjestelmä voidaan sovittaa, joka järjestelmä käsittää järjestelmäoskillaattorin järjestelmän pääkellosignaalin tarjoamiseksi, ohjauslohkon ainakin digitaalijärjestelmän tehonhallinnan ohjaamiseksi ja yhden tai useampia toiminnallisia lohkoja, joista ainakin yksi on järjestetty havaitsemaan tarpeen järjestelmäkellolle. Ainakin yksi toiminnallinen lohko on järjestetty lähettämään ainakin yhden järjestelmäkellopyynnön ohjauslohkoon, joka puolestaan on järjestetty käynnistämään järjestelmäoskillaattori järjestelmäkellosignaalin tarjoamiseksi vasteena järjestelmäkellon pyyntösignaalin vastaanottamiselle. Kun järjestelmäkellosignaali ilmestyy, mainittu ainakin yksi toiminnallinen lohko on järjestetty havaitsemaan järjestelmäkellosignaalin. (Kuvio 2)
FI20040418A 2004-03-18 2004-03-18 Digitaalijärjestelmän kellokontrolli FI20040418L (fi)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FI20040418A FI20040418L (fi) 2004-03-18 2004-03-18 Digitaalijärjestelmän kellokontrolli
US11/059,741 US20050210301A1 (en) 2004-03-18 2005-02-17 Digital system clock control
EP05717337A EP1738241A1 (en) 2004-03-18 2005-03-16 Digital system clock control
PCT/FI2005/050084 WO2005088423A1 (en) 2004-03-18 2005-03-16 Digital system clock control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20040418A FI20040418L (fi) 2004-03-18 2004-03-18 Digitaalijärjestelmän kellokontrolli

Publications (3)

Publication Number Publication Date
FI20040418A0 FI20040418A0 (fi) 2004-03-18
FI20040418A7 true FI20040418A7 (fi) 2005-09-19
FI20040418L FI20040418L (fi) 2005-09-19

Family

ID=32039437

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20040418A FI20040418L (fi) 2004-03-18 2004-03-18 Digitaalijärjestelmän kellokontrolli

Country Status (4)

Country Link
US (1) US20050210301A1 (fi)
EP (1) EP1738241A1 (fi)
FI (1) FI20040418L (fi)
WO (1) WO2005088423A1 (fi)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0801523D0 (en) * 2008-01-28 2008-03-05 Cambridge Silicon Radio Ltd Integrated signal receiver
US8392745B2 (en) * 2010-04-26 2013-03-05 Broadcom Corporation Modular integrated circuit with clock control circuit
US8683270B2 (en) * 2010-04-29 2014-03-25 Micron Technology, Inc. Signal line to indicate program-fail in memory
US9491345B2 (en) 2014-03-28 2016-11-08 Intel Corporation Adjustment of flash device based on temperature

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63163912A (ja) * 1986-12-26 1988-07-07 Toshiba Corp マイクロコンピユ−タシステム
US6163848A (en) * 1993-09-22 2000-12-19 Advanced Micro Devices, Inc. System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus
US5586270A (en) * 1993-09-30 1996-12-17 Intel Corporation Method and apparatus for upgrading a central processing unit and existing memory structure in a computer system
JP3505018B2 (ja) * 1994-11-22 2004-03-08 株式会社ルネサステクノロジ 半導体集積回路
JPH11202968A (ja) * 1998-01-20 1999-07-30 Mitsubishi Electric Corp マイクロコンピュータ
JP2000066759A (ja) * 1998-08-17 2000-03-03 Oki Electric Ind Co Ltd クロック制御回路
US6735454B1 (en) * 1999-11-04 2004-05-11 Qualcomm, Incorporated Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode
DE60211921T2 (de) * 2001-08-29 2006-10-05 Analog Devices Inc., Norwood Architektur und system von einem generischen seriellen port
JP3665030B2 (ja) * 2002-02-19 2005-06-29 Ｎｅｃマイクロシステム株式会社 バス制御方法及び情報処理装置
US6934870B1 (en) * 2002-02-21 2005-08-23 Cisco Technology, Inc. Clock management scheme for PCI and cardbus cards for power reduction
GB2386794A (en) * 2002-03-22 2003-09-24 Zarlink Semiconductor Ltd Power saving in a peripheral device
US6691071B2 (en) * 2002-05-13 2004-02-10 Motorola, Inc. Synchronizing clock enablement in an electronic device
US7362188B2 (en) * 2003-06-04 2008-04-22 Texas Instruments Incorporated System-on-a-chip (SoC) clock management—a scalable clock distribution approach
US20050232218A1 (en) * 2004-04-19 2005-10-20 Broadcom Corporation Low-power operation of systems requiring low-latency and high-throughput

Also Published As

Publication number Publication date
FI20040418L (fi) 2005-09-19
FI20040418A0 (fi) 2004-03-18
EP1738241A1 (en) 2007-01-03
US20050210301A1 (en) 2005-09-22
WO2005088423A1 (en) 2005-09-22

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Legal Events

Date Code Title Description
FD Application lapsed