ES8605341A1 - Circuito de interfase uso en un sistema de comunicacion telefonica. - Google Patents
Circuito de interfase uso en un sistema de comunicacion telefonica.Info
- Publication number
- ES8605341A1 ES8605341A1 ES532629A ES532629A ES8605341A1 ES 8605341 A1 ES8605341 A1 ES 8605341A1 ES 532629 A ES532629 A ES 532629A ES 532629 A ES532629 A ES 532629A ES 8605341 A1 ES8605341 A1 ES 8605341A1
- Authority
- ES
- Spain
- Prior art keywords
- bus
- interface circuit
- processor
- control channel
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012544 monitoring process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
CIRCUITO DE INTERFASE PARA USO EN UN SISTEMA DE COMUNICACION TELEFONICA. COMPRENDE UNA CIRCUITERIA PARA INTERFASAR EL CONTROLADOR D EMICROPROCESADOR CON LOS MODULOS DE CIRCUITO DE LA INTERFASE DE CONTROL (203) COMO EL CIRCUITO DE RETENCION DE DIRECCIONES (65) Y EL CIRCUITO DE RETENCION DE ESTADOS (45); UNA INTERFASE DE MICROPROCESADOR (10) QUE COMPRENDE UNA CIRCUITERIA PARA QUE PASEN LOS DATOS DEL CIRCUITO DE RETENCION DE ENTRADA TDBI (20) EN 6 BYTES DE 8 BITIOS DE LONGITUD POR EL BUS DE CONDUCTORES MULTIPLES (MBI) AL CONTROLADOR DE MICROPROCESADOR; DONDE LA INTERFASE DE MICROPROCESADOR (10) TRANSFIERE TAMBIEN INFORMACION DE CONTROL DESDE EL CONTROLADOR DE MICROPROCESADOR AL CIRCUITO DE RETENCION DE SALIDA (TDM 30).
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/496,483 US4511969A (en) | 1983-05-20 | 1983-05-20 | Control channel interface circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ES532629A0 ES532629A0 (es) | 1986-03-16 |
| ES8605341A1 true ES8605341A1 (es) | 1986-03-16 |
Family
ID=23972834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES532629A Expired ES8605341A1 (es) | 1983-05-20 | 1984-05-18 | Circuito de interfase uso en un sistema de comunicacion telefonica. |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US4511969A (es) |
| JP (1) | JP2653777B2 (es) |
| AU (1) | AU569081B2 (es) |
| CA (1) | CA1223323A (es) |
| DE (2) | DE3490263C2 (es) |
| ES (1) | ES8605341A1 (es) |
| FR (1) | FR2546354B1 (es) |
| GB (1) | GB2149999B (es) |
| IT (1) | IT1176151B (es) |
| WO (1) | WO1984004833A1 (es) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8430004D0 (en) * | 1984-11-28 | 1985-01-09 | Plessey Co Plc | Microprocessor interface device |
| GB8508740D0 (en) * | 1985-04-03 | 1985-05-09 | Plessey Co Plc | Switching arrangements |
| GB8601545D0 (en) * | 1986-01-22 | 1986-02-26 | Stc Plc | Data transmission equipment |
| DE3634019A1 (de) * | 1986-10-06 | 1988-04-14 | Man Technologie Gmbh | Vorrichtung und verfahren zum seriellen datenaustausch zwischen mehr als zwei teilnehmern |
| US4958342A (en) * | 1987-03-11 | 1990-09-18 | Aristacom International, Inc. | Adaptive digital network interface |
| US4882727A (en) * | 1987-03-11 | 1989-11-21 | Aristacom International, Inc. | Adaptive digital network interface |
| US4890254A (en) * | 1987-03-11 | 1989-12-26 | Aristacom International, Inc. | Clock disabling circuit |
| US5146605A (en) * | 1987-11-12 | 1992-09-08 | International Business Machines Corporation | Direct control facility for multiprocessor network |
| US4916692A (en) * | 1988-03-14 | 1990-04-10 | Racal Data Communications Inc. | TDM bus controller |
| US5625842A (en) * | 1988-05-18 | 1997-04-29 | Zilog, Inc. | System for the automatic transfer of message status in digital data communication |
| JPH01300361A (ja) * | 1988-05-28 | 1989-12-04 | Nec Eng Ltd | マイクロプロセッサシステム |
| US5193179A (en) * | 1988-08-09 | 1993-03-09 | Harris Corporation | Activity monitor system non-obtrusive statistical monitoring of operations on a shared bus of a multiprocessor system |
| US5123092A (en) * | 1988-10-21 | 1992-06-16 | Zenith Data Systems Corporation | External expansion bus interface |
| US4935868A (en) * | 1988-11-28 | 1990-06-19 | Ncr Corporation | Multiple port bus interface controller with slave bus |
| US5303351A (en) * | 1988-12-30 | 1994-04-12 | International Business Machines Corporation | Error recovery in a multiple 170 channel computer system |
| CA2008071A1 (en) * | 1989-01-27 | 1990-07-27 | Jeffrey S. Watters | Pump bus to avoid indeterminacy in reading variable bit field |
| US5276678A (en) * | 1990-06-18 | 1994-01-04 | Intelect, Inc. | Distributed switching and telephone conferencing system |
| US5410654A (en) * | 1991-07-22 | 1995-04-25 | International Business Machines Corporation | Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals |
| US5493581A (en) * | 1992-08-14 | 1996-02-20 | Harris Corporation | Digital down converter and method |
| US5495585A (en) * | 1992-10-16 | 1996-02-27 | Unisys Corporation | Programmable timing logic system for dual bus interface |
| US5509127A (en) * | 1992-12-04 | 1996-04-16 | Unisys Corporation | Transmission logic apparatus for dual bus network |
| US5442754A (en) * | 1992-12-04 | 1995-08-15 | Unisys Corporation | Receiving control logic system for dual bus network |
| US5497373A (en) * | 1994-03-22 | 1996-03-05 | Ericsson Messaging Systems Inc. | Multi-media interface |
| US5940402A (en) * | 1997-06-06 | 1999-08-17 | Timeplex, Inc. | Method and apparatus for TDM interrupt transmissions between multiple devices and a processor |
| US6594735B1 (en) | 1998-12-28 | 2003-07-15 | Nortel Networks Limited | High availability computing system |
| JP2002108804A (ja) * | 2000-10-04 | 2002-04-12 | Nec Eng Ltd | データスイッチング装置 |
| US7359882B2 (en) * | 2001-05-11 | 2008-04-15 | Bea Systems, Inc. | Distributed run-time licensing |
| US7707339B2 (en) * | 2007-12-18 | 2010-04-27 | Freescale Semiconductor, Inc. | Data arbitration on a bus to determine an extreme value |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3632881A (en) * | 1970-03-16 | 1972-01-04 | Ibm | Data communications method and system |
| FR2328349A1 (fr) * | 1973-03-01 | 1977-05-13 | Ibm France | Systeme de commutation en multiplex a division dans le temps |
| US3932841A (en) * | 1973-10-26 | 1976-01-13 | Raytheon Company | Bus controller for digital computer system |
| US3921137A (en) * | 1974-06-25 | 1975-11-18 | Ibm | Semi static time division multiplex slot assignment |
| US4161786A (en) * | 1978-02-27 | 1979-07-17 | The Mitre Corporation | Digital bus communications system |
| US4223380A (en) * | 1978-04-06 | 1980-09-16 | Ncr Corporation | Distributed multiprocessor communication system |
| JPS6041372B2 (ja) * | 1979-07-19 | 1985-09-17 | 株式会社明電舎 | 複数のデ−タ処理装置の接続方式 |
| CA1143812A (en) * | 1979-07-23 | 1983-03-29 | Fahim Ahmed | Distributed control memory network |
| US4251880A (en) * | 1979-07-31 | 1981-02-17 | Bell Telephone Laboratories, Incorporated | Digital loop switch for controlling data information having differing transmission characteristics |
| US4280217A (en) * | 1979-12-26 | 1981-07-21 | Bell Telephone Laboratories, Incorporated | Time division switching system control arrangement |
| US4331835A (en) * | 1980-10-29 | 1982-05-25 | Siemens Corporation | Interface unit for a modular telecommunication system |
| JPS6022384B2 (ja) * | 1980-12-29 | 1985-06-01 | パナフアコム株式会社 | バス変換方式 |
| US4442502A (en) * | 1981-03-30 | 1984-04-10 | Datapoint Corporation | Digital information switching system |
| FR2503497B1 (fr) * | 1981-04-03 | 1988-07-08 | Telephonie Ind Commerciale | Systeme temporel de telecommunications |
-
1983
- 1983-05-20 US US06/496,483 patent/US4511969A/en not_active Expired - Lifetime
-
1984
- 1984-04-16 DE DE3490263A patent/DE3490263C2/de not_active Expired - Fee Related
- 1984-04-16 AU AU28658/84A patent/AU569081B2/en not_active Ceased
- 1984-04-16 DE DE19843490263 patent/DE3490263T1/de active Pending
- 1984-04-16 WO PCT/US1984/000571 patent/WO1984004833A1/en not_active Ceased
- 1984-04-16 GB GB08500955A patent/GB2149999B/en not_active Expired
- 1984-04-16 JP JP59501815A patent/JP2653777B2/ja not_active Expired - Lifetime
- 1984-04-18 CA CA000452258A patent/CA1223323A/en not_active Expired
- 1984-05-16 FR FR8407579A patent/FR2546354B1/fr not_active Expired
- 1984-05-18 ES ES532629A patent/ES8605341A1/es not_active Expired
- 1984-05-18 IT IT21009/84A patent/IT1176151B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2653777B2 (ja) | 1997-09-17 |
| AU2865884A (en) | 1984-12-18 |
| IT8421009A1 (it) | 1985-11-18 |
| DE3490263T1 (de) | 1985-06-13 |
| FR2546354B1 (fr) | 1988-11-25 |
| ES532629A0 (es) | 1986-03-16 |
| FR2546354A1 (fr) | 1984-11-23 |
| IT1176151B (it) | 1987-08-18 |
| WO1984004833A1 (en) | 1984-12-06 |
| CA1223323A (en) | 1987-06-23 |
| IT8421009A0 (it) | 1984-05-18 |
| GB8500955D0 (en) | 1985-02-20 |
| DE3490263C2 (de) | 1996-04-25 |
| US4511969A (en) | 1985-04-16 |
| GB2149999A (en) | 1985-06-19 |
| GB2149999B (en) | 1986-09-10 |
| JPS61500043A (ja) | 1986-01-09 |
| AU569081B2 (en) | 1988-01-21 |
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