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ES544405A0 - Procedimiento para la fabricacion de placas de circuito impreso de capas multiples. - Google Patents

Procedimiento para la fabricacion de placas de circuito impreso de capas multiples.

Info

Publication number
ES544405A0
ES544405A0 ES544405A ES544405A ES544405A0 ES 544405 A0 ES544405 A0 ES 544405A0 ES 544405 A ES544405 A ES 544405A ES 544405 A ES544405 A ES 544405A ES 544405 A0 ES544405 A0 ES 544405A0
Authority
ES
Spain
Prior art keywords
procedure
manufacture
printed circuit
multiple layers
circuit plates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES544405A
Other languages
English (en)
Other versions
ES8701453A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
President Engineering Corp
Original Assignee
President Engineering Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by President Engineering Corp filed Critical President Engineering Corp
Publication of ES8701453A1 publication Critical patent/ES8701453A1/es
Publication of ES544405A0 publication Critical patent/ES544405A0/es
Expired legal-status Critical Current

Links

Classifications

    • H10P14/68—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10598—Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Details Of Indoor Wiring (AREA)
ES544405A 1984-06-22 1985-06-21 Procedimiento para la fabricacion de placas de circuito impreso de capas multiples. Expired ES8701453A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843423181 DE3423181A1 (de) 1984-06-22 1984-06-22 Verfahren zur herstellung von vorlaminaten fuer mehrlagenleiterplatten

Publications (2)

Publication Number Publication Date
ES8701453A1 ES8701453A1 (es) 1986-11-16
ES544405A0 true ES544405A0 (es) 1986-11-16

Family

ID=6238964

Family Applications (1)

Application Number Title Priority Date Filing Date
ES544405A Expired ES8701453A1 (es) 1984-06-22 1985-06-21 Procedimiento para la fabricacion de placas de circuito impreso de capas multiples.

Country Status (18)

Country Link
EP (1) EP0167867A3 (es)
JP (1) JPS6169197A (es)
KR (1) KR860000711A (es)
AU (1) AU4395185A (es)
BR (1) BR8502956A (es)
CA (1) CA1224884A (es)
DD (1) DD234643A5 (es)
DE (1) DE3423181A1 (es)
DK (1) DK278185A (es)
ES (1) ES8701453A1 (es)
FI (1) FI852464A7 (es)
GR (1) GR851516B (es)
HU (1) HUT39311A (es)
IL (1) IL75551A0 (es)
NO (1) NO852512L (es)
PL (1) PL254118A1 (es)
PT (1) PT80686B (es)
ZA (1) ZA854662B (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801489A (en) * 1986-03-13 1989-01-31 Nintendo Co., Ltd. Printed circuit board capable of preventing electromagnetic interference
JPS62295488A (ja) * 1986-06-14 1987-12-22 松下電工株式会社 多層プリント配線板の製法
DE3819785A1 (de) * 1988-06-10 1989-12-14 Ferrozell Sachs & Co Gmbh Verfahren zum herstellen von mehrlagigen, gedruckten leiterplatten
CH678412A5 (es) * 1988-11-11 1991-09-13 Fela Planungs Ag
SE9001766L (sv) * 1990-05-16 1991-09-02 Perstorp Ab Saett vid tillverkning av flerlagermoensterkort
US5832596A (en) * 1996-12-31 1998-11-10 Stmicroelectronics, Inc. Method of making multiple-bond shelf plastic package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196598A (en) * 1981-05-29 1982-12-02 Hitachi Ltd Method of producing multilayer printed board

Also Published As

Publication number Publication date
PT80686A (de) 1985-07-01
EP0167867A2 (de) 1986-01-15
CA1224884A (en) 1987-07-28
DE3423181A1 (de) 1986-01-02
PL254118A1 (en) 1986-05-06
GR851516B (es) 1985-11-25
IL75551A0 (en) 1985-10-31
PT80686B (de) 1987-02-12
HUT39311A (en) 1986-08-28
EP0167867A3 (de) 1987-01-28
ES8701453A1 (es) 1986-11-16
ZA854662B (en) 1986-04-30
AU4395185A (en) 1986-01-02
DK278185D0 (da) 1985-06-19
FI852464A0 (fi) 1985-06-20
KR860000711A (ko) 1986-01-30
FI852464L (fi) 1985-12-23
FI852464A7 (fi) 1985-12-23
JPS6169197A (ja) 1986-04-09
NO852512L (no) 1985-12-23
DD234643A5 (de) 1986-04-09
DK278185A (da) 1985-12-23
BR8502956A (pt) 1986-03-04

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