EP1958102A1

EP1958102A1 - Method for providing an ic design and ic design tool

Info

Publication number: EP1958102A1
Application number: EP06831983A
Authority: EP
Inventors: Jean-Francois Lepere
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2005-12-02
Filing date: 2006-11-28
Publication date: 2008-08-20
Also published as: CN101317180A; WO2007063495A1; JP2009517759A

Abstract

A method for providing an IC design having a core functionality, an IO (input/output) ring surrounding the core functionality and a boundary scan architecture for providing access to the core functionality or the IO ring during a predefined mode of the integrated circuit, and a design tool implementing this method are disclosed. The method comprises a step (110) of providing a first netlist of the core functionality and the IO ring followed by a step (120, 130) of specifying a boundary scan design for inclusion in the first netlist. Next, a second netlist from the first netlist and the boundary scan design specification is synthesized (150), from which the instances of boundary scan design are isolated (420). In a separate step (410), a third netlist of the core functionality without the IO ring is provided, which is combined with the isolated boundary scan elements into a fourth netlist in a subsequent step (460). In a final step (470), a description of the IO ring is added to the fourth netlist. The integration of the boundary scan elements into the core netlist facilitates replacement of the IO ring in the IC design without the need to regenerate the boundary scan design.

Description

DESCRIPTION

METHOD FOR PROVIDING AN IC DESIGN AND IC DESIGN TOOL

The present invention relates to a method of providing a design of an integrated circuit having a core functionality, an IO (input/output) ring surrounding the core functionality and a boundary scan architecture for providing access to the core functionality during a predefined mode of the integrated circuit.

The present invention further relates to a design tool for providing a design of an integrated circuit having a core functionality, an IO (input/output) ring surrounding the core functionality and a boundary scan architecture for providing access to the core functionality or the IO ring during a predefined mode of the integrated circuit.

Nowadays, many digital integrated circuits (ICs) comprise some form of boundary scan functionality, which is defined in the IEEE 1149.1 or JTAG standard, for providing access to parts of the IC in predefined modes of the IC. The boundary scan functionality may be used in a test mode of the IC either to test the IO connections of the IC or to shift test bit patterns, i.e. test vectors, to and from the internals of the IC to test the internals, such as a core module, of the IC. Consequently, the boundary scan functionality typically is physically located between the internals of the IC and its IO ring. An example of such use can be found in US patent US6774672, in which a field programmable gate array (FPGA) is disclosed, which comprises a boundary scan chain surrounding the FPGA tiles for providing high-level test access to those tiles.

Alternatively, boundary scan functionality may be used in a programming mode of the IC to shift programming data to the internals of the IC via the boundary scan test access port (TAP) under control of the TAP controller. Existing IC design tools such as BSD Compiler™ from Synopsys and BSD Architect™ from Mentor Graphics can routinely add boundary scan functionality to an IC design. A typical example of the boundary scan insertion method implemented by such a tool is given in Fig. 1. In step 110, a netlist, e.g. a register transfer level (RTL) netlist is read in by the tool. Such a netlist is typically provided by the user of the tool. In a next step 120, the user defines the boundary scan specification, after which the tool generates an IC design including a boundary scan design in step 130. In step 140, the design constraints for the IC design are set by the user, e.g. timing constraints, area constraints and so on, after which the tool synthesizes a gate level netlist of the IC design in a step 150. This gate level netlist may be written to file in step 160.

Subsequently, the compliance of the gate level IC design, or more particularly, the boundary scan design part of the IC design, with the IEEE 1149.1 standard specifications is checked by the tool in step 170. If the design does not comply, the user may return to step 120 or step 140 to rectify the error(s) in the design. If the gate level design is found to be IEEE1149.1 compliant, test vectors are generated, if not present, and inserted into the design in step 180, after which the behaviour of the design is simulated using the test vectors in step 190.

Fig. 2 gives a schematic overview of the effect of such a method on an IC design. The netlist provided to the design tool in step 110 typically is an RTL netlist 200 comprising a description of a core 202 and an IO ring comprising IO elements 204, e.g. IO pads and voltage level shifters. Execution of steps 110, 120 and 130 leads to a netlist 210 in which the core 202 is unmodified, and in which boundary scan elements, e.g. a boundary scan chain 206 and a boundary scan TAP 208 are inserted into the modified IO ring 214. Thus, the resulting netlist 210 includes a plurality of boundary scan elements that are integrated in the IC design external to the core of the IC.

A drawback of the existing tools is that they do not facilitate the facile reuse of parts of the netlist 210. Such reuse is for instance advantageous where different versions of an IC have to be produced, for instance in cases where different customers have different voltage interface requirements, for which different IO rings may have to be used. With the present tools, the flow of Fig. 1 will have to be re-executed in its entirety to generate the different version of the IC, which is a time-consuming exercise.

The present invention seeks to provide a method according to the opening paragraph that enables more facile IC redesign.

The present invention seeks to provide an IC design tool according to the opening paragraph that enables more facile IC redesign.

According to a first aspect of the present invention, there is provided a method of providing a design of an integrated circuit having a core functionality, an IO (input/output) ring surrounding the core functionality and a boundary scan architecture for providing access to the core functionality or the IO ring during a predefined mode of the integrated circuit, the method comprising providing a first netlist of the core functionality and the IO ring; specifying a boundary scan design for inclusion in the first netlist; synthesizing a second netlist from the first netlist and the boundary scan design specification; isolating the boundary scan elements from the second netlist; providing a third netlist of the core functionality without the IO ring; combining the third netlist and the isolated boundary scan elements into a fourth netlist; and generating a fifth netlist by adding a description of the IO ring to the fourth netlist.

This has the advantage that a netlist is obtained in which the boundary scan elements are included in, or at least added to, the core functionality. Consequently, this netlist can be reused in case a version of the IC with modified IO behaviour has to be designed. To facilitate reuse of the core design, the method further comprises the step writing the fourth netlist to a first file. The first file can be used as an input file for the redesign of the IC.

Typically, the first netlist and the third netlist are register transfer level netlists and the second netlist and the fourth netlist are gate level netlists, although the method may also use alternative descriptions of the various stages in the IC design, e.g. descriptions at different abstraction levels.

Preferably, the method further comprises checking compliance of the second netlist with the boundary scan standard; generating test patterns from the second netlist; and generating a test result for the fifth netlist by testing the fifth netlist with the test patterns. This way, it is verified that the fifth netlist does not contain any errors such as interconnection faults that may be introduced in the step of generating the fourth netlist or adding the IO ring to the fourth netlist.

Advantageously, the method further comprises generating a test result for the second netlist by testing the second netlist with the test patterns; and comparing the test result of the fifth netlist with the test result of the second netlist. The comparison of the simulated behaviour of the fifth netlist to that of the second netlist simplifies the verification of the fifth netlist.

According to a further aspect of the present invention, there is provided a design tool for providing a design of an integrated circuit having a core functionality, an IO (input/output) ring surrounding the core functionality and a boundary scan architecture for providing access to the core functionality or the IO ring during a predefined mode of the integrated circuit, the design tool comprising means for providing a first netlist of the core functionality and the IO ring; means for specifying a boundary scan design for inclusion in the first netlist; means for synthesizing a second netlist from the first netlist and the boundary scan design specification; means for isolating the boundary scan elements from the second netlist; means for providing a third netlist of the core functionality without the IO ring; means for combining the third netlist and the isolated boundary scan elements into a fourth netlist; and means for generating a fifth netlist by adding a description of the IO ring to the fourth netlist.

The design tool of the present invention implements the method of the present invention, e.g. by means of suitable algorithms that will be apparent to the skilled person, and therefore benefits from the same advantageous aspects as the method of the present invention. Advantageously, the design tool comprises means for writing the fourth netlist to a first file for enabling reuse of the fourth netlist. This facilitates reuse of the fourth netlist in redesigns of the IC. The first file may be stored on a computer readable medium, e.g. a memory device, hard-drive, CD-ROM, DVD and so on either in isolation or as part of an IC design library that holds instances of IC building blocks to facilitate distribution of the first file. The design tool itself may also be stored on such a computer-readable medium to facilitate distribution of the tool.

The invention is described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein:

Fig. 1 depicts an example of a known method for inserting boundary scan functionality into an IC design;

Fig. 2 schematically depicts a conceptual layout of an IC design obtained with the known method;

Fig. 3 depicts a flowchart of an embodiment of the method of the present invention; and

Fig. 4 schematically depicts a key concept of the method of the present invention.

It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures and their detailed description to indicate the same or similar parts.

Fig. 3 schematically depicts the design concept implemented by the method of the present invention. In a first step, a netlist 200 having a core 202 and an IO ring 204 is manipulated to add a boundary scan design to the netlist 200. This can be performed with steps 120, 130, 140 and 150 of the method as shown in Fig. 1 , which has been previously described. The result is a netlist 210, which includes an unmodified core 202, a boundary scan chain (BSC) 206, a test access port (TAP) 208 and a modified IO ring 214. The IO ring is considered to be modified because it now includes the boundary scan elements 206 and 208. Consequently, replacement of the IO ring 214 with the prior art methods includes the replacement, i.e. redesign, of the boundary scan elements 206 and 208, which means that the redesign effort is a time- consuming operation.

The required redesign effort is reduced by the method of the present invention in the following way. The instances of the boundary scan elements, e.g. BSC 206 and TAP 208 are identified in the netlist 210 and isolated from this netlist, e.g. by copying them. This can be realized by known search algorithms; for instance, the instances of the elements of the boundary scan design may have an instance name or another instance property that is unique to the boundary scan elements and which is used as a label by which these instances in the netlist 210 are identified. Other ways of identifying such instances will be apparent to those skilled in the art.

The isolated instances of the boundary scan elements, e.g. BSC 206 and TAP 208, are added to a netlist that describes the IC core 202 in isolation. The result is a netlist 320, which comprises a modified core 232 in the sense that the BSC 206 and TAP 208 form a part of the core 232. The netlist 320 can be used as a starting point for the generation of the desired IC design by the simple addition of an IO ring 204 to the netlist 320, thus resulting in the netlist 330. It will be appreciated that netlist 320 can be used as a starting point for the generation of different versions of the desired IC design, for instance by simply adding different versions of the IO ring 204 to the netlist 320 without the need to regenerate the boundary scan architecture for each of these different versions of the IC design.

At this point, it is emphasized that the instances of the boundary scan elements in the circuit design are not strictly required to comply with the IEEE 1149.1 standard; for instance, a scan chain may be introcuced without the presence of a TAP controller, or a TAP controller may be introduced without the presence of a boundary scan register and so on. In case of a non- compliant boundary scan design, step 170 may be omitted from the method of the present invention. Fig. 4 shows a preferred embodiment of a flow of the method of the present invention, which implements the design concept shown in Fig. 3. The preferred embodiment of the present invention extends the method depicted in Fig. 1 by grouping, or isolating, in a step 420, the instances of the boundary scan design from the IC design generated in step 150. The grouped, or isolated, instances of the boundary scan design, e.g. BSC 206 and TAP 208, may be written to a file in a step 425. In addition, an RTL netlist is provided of the core 202 in isolation in a step 410, and the RTL netlist of the core in isolation and the grouped instances of the boundary scan design are interconnected in step 430. It is emphasized that the combination of two netlist portions such as an RTL netlist with a gate level netlist or the combination of two gate level netlists, is standard functionality in existing IC design tools, and will not be further explained for that reason.

In step 440, the design constraints for this IC design are set in analogy with step 140, after which a gate level netlist of the IC design conforming to the set design constraints is generated in step 450. This gate level netlist, which includes a gate level description of the modified core 232, may be written to a file in step 460 of the method. This file may be used for the generation of various IC designs, for instance the generation of IC designs having different IO rings. Finally, in step 470, the IO ring is added to the design of the modified core 232.

The correctness of the design generated in step 470 may be validated by simulating the operation of the IC design in step 190 using the test vectors generated in step 180. The test simulation results of the design of step 470 may be evaluated in isolation, or may be compared to the simulation results of a simulation of the operation of the design synthesized in step 150 using the test vectors generated in step 180.

It will be apparent to those skilled in the art that modifications to this flow, e.g. the manipulation of netlists at different abstraction levels than those shown in Fig. 4, can be readily made without the need for inventive skill.

The above-described method of the present invention may be implemented in an IC design tool, e.g. a computer aided design (CAD) tool. Because the various steps of the method of the present invention can be implemented in such a tool using functionality, i.e. algorithms, that is already available in such a tool, this implementation is straightforward to the skilled person and does not require further explanation for this reason. Such a design tool may be provided in the form of a software package on a suitable computer-readable medium such as a DVD, CD-ROM, memory stick and so on.

Also, the file generated in step 460 of the method of the present invention, i.e. the (gate-level) netlist of the modified core 232 including the instances of the boundary scan design, may be provided on such a computer- readable medium to facilitate rapid distribution of such a design. The file may be one of a plurality of files on said medium, the plurality of files forming a design library for use with a design tool of the present invention.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of providing a design of an integrated circuit having a core functionality (202), an IO (input/output) ring (204) surrounding the core functionality and a boundary scan architecture (206, 208) for providing access to the core functionality (202) or the IO ring (204) during a predefined mode of the integrated circuit, the method comprising: providing (110) a first netlist (200) of the core functionality (202) and the IO ring (204); specifying (120, 130, 140) a boundary scan design (206, 208) for inclusion in the first netlist (200); synthesizing (150) a second netlist (210) from the first netlist (200) and the boundary scan design specification; isolating (420) the boundary scan design elements (206, 208) from the second netlist (210); providing (410) a third netlist of the core functionality (202) without the IO ring; combining (430, 440, 450) the third netlist and the isolated boundary scan elements (206, 208) into a fourth netlist (320); and generating a fifth netlist (330) adding a description of the IO ring (204) to the fourth netlist (320).

2. A method as claimed in claim 1 , further comprising writing (460) the fourth netlist (320) to a first file for enabling reuse of the fourth netlist (320).

3. A method as claimed in claim 1 or 2, wherein the first netlist (200) and the third netlist are register transfer level netlists and the second netlist (210) and the fourth netlist (320) are gate level netlists.

4. A method as claimed in claim 1 , further comprising: checking compliance (170) of the second netlist (210) with the boundary scan standard; generating (180) test patterns from the second netlist (210); and generating a test result for the fifth netlist (330) by testing (190) the fifth netlist with the test patterns.

5. A method as claimed in claim 4, further comprising: generating a test result for the second netlist (210) by testing (190) the second netlist (210) with the test patterns; and comparing the test result of the fifth netlist (330) with the test result of the second netlist (210).

6. A design tool for providing a design of an integrated circuit having a core functionality (202), an IO (input/output) ring (204) surrounding the core functionality and a boundary scan architecture (206, 208) for providing access to the core functionality (202) or the IO ring (204) during a predefined mode of the integrated circuit, the design tool comprising: means for providing (110) a first netlist (200) of the core functionality (202) and the IO ring (204); means for specifying (120, 130, 140) a boundary scan design (206, 208) for inclusion in the first netlist (200); means for synthesizing (150) a second netlist (210) from the first netlist (200) and the boundary scan design specification; means for isolating (420) the boundary scan design elements (206, 208) from the second netlist (210); means for providing (410) a third netlist of the core functionality (202) without the IO ring; means for combining (430, 440, 450) the third netlist and the isolated boundary scan elements (206, 208) into a fourth netlist (320); and means for generating a fifth netlist (330) adding a description of the IO ring (204) to the fourth netlist (320).

7. A design tool as claimed in claim 6, further comprising means for writing (460) the fourth netlist (320) to a first file for enabling reuse of the fourth netlist (320).

8. A computer readable medium comprising the first file generated by the design tool of claim 7.

9. A computer readable medium comprising a file library including the first file generated by the design tool of claim 7.

10. A computer readable medium comprising the design tool of claim 6 or 7.