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EP1728269A1 - Method for making a field-effect transistor with diamond-like carbon channel and resulting transistor - Google Patents

Method for making a field-effect transistor with diamond-like carbon channel and resulting transistor

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Publication number
EP1728269A1
EP1728269A1 EP05744607A EP05744607A EP1728269A1 EP 1728269 A1 EP1728269 A1 EP 1728269A1 EP 05744607 A EP05744607 A EP 05744607A EP 05744607 A EP05744607 A EP 05744607A EP 1728269 A1 EP1728269 A1 EP 1728269A1
Authority
EP
European Patent Office
Prior art keywords
layer
channel
transistor
diamond
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05744607A
Other languages
German (de)
French (fr)
Inventor
Simon Deleonibus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1728269A1 publication Critical patent/EP1728269A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond

Definitions

  • the invention relates to a method for producing a field effect transistor comprising a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator, the channel being constituted by a carbon layer. diamond.
  • a field effect transistor has a source and a drain which are connected by a channel.
  • a gate electrode separated from the channel by a gate insulator, makes it possible to control the conduction state of the channel.
  • the source, the drain and the channel of the field effect transistors are made from semiconductor material, for example silicon.
  • CMOS type inverter For the production of a CMOS type inverter, a PMOS type transistor and an NMOS type transistor are assembled. Optimal operation of the inverter requires that the saturation current in the PMOS transistor be equal to the saturation current in the NMOS transistor.
  • the electric current flowing through the channel In an NMOS transistor, the electric current flowing through the channel is an electron current, while in a PMOS transistor, the electric current flowing through the channel is a hole current.
  • the current is proportional to the mobility of the corresponding charge carriers. Since the mobility of electrons in silicon is greater than the mobility of holes in silicon, the dimensions of the NMOS and PMOS transistors are adapted so as to obtain equal saturation currents in the NMOS and PMOS transistors.
  • the PMOS transistor of a CMOS inverter for example, has a channel width greater than the channel width of the associated NMOS transistor. The miniaturization of the CMOS inverter is then limited by the dimensions of the PMOS transistor.
  • Field effect transistors having diamond channels are well known.
  • a P-doped semiconductor diamond layer forms a channel.
  • a source and a drain are formed by N-doped semiconductor diamond layers.
  • a diamond gate insulator is placed on the channel and a gate electrode is placed on this gate insulator.
  • the document US Pat. No. 5,107,315 also describes a transistor having an N-doped channel and P-doped source and drain. The fabrication of the transistor consists in successively making the channel, the source and drain, the gate insulator and the gate. Such a transistor may have parasitic capacitances between drain and gate and between source and gate, which deteriorates the performance of the transistor.
  • the object of the invention is to remedy these drawbacks and in particular to make it possible to produce transistors and logic gates of small dimensions having low parasitic capacities.
  • the method successively comprises the deposition of a layer of diamond carbon on a substrate, depositing a gate insulating layer on the diamond carbon layer, depositing, on the gate insulating layer, at least one conductive layer and its etching, so as to form the gate electrode, depositing 'an insulating material on the sides of the gate electrode to constitute a lateral insulator, the etching of the insulating gate layer, the etching of the diamond carbon layer so as to delimit the channel, the deposition, on both sides and 'other of the channel, a semiconductor material intended to constitute the source and a semiconductor material intended to constitute the drain.
  • Another object of the invention is a transistor obtained by the method according to the invention and a CMOS type logic gate comprising such transistors.
  • FIG. 1 to 5 illustrate a particular embodiment of a method for producing a transistor according to the invention.
  • FIG. 6 schematically represents a CMOS inverter comprising transistors according to the invention. Description of particular embodiments
  • the field effect transistor according to the invention comprises a channel formed by a diamond carbon layer.
  • the channel can be doped with N type dopants to form a PMOS type transistor or P type dopants to form an NMOS type transistor.
  • N type dopants for a doping of 10 15 atoms per cubic centimeter, diamond carbon has, at room temperature, an electron mobility of 1800cm 2 / Vs and a hole mobility of 1800cm 2 / Vs.
  • a layer 1 of diamond carbon is deposited on a substrate 2, as shown in FIG. 1.
  • the substrate may comprise, on its surface, a thin insulating layer, for example an oxide layer having a high dielectric constant , for example alumina.
  • an insulating grid layer 3 is deposited on the diamond carbon layer 1.
  • a conductive layer 4 is deposited on the insulating grid layer 3.
  • the conductive layer 4 can be constituted by the superposition of a first conductive layer 4a and a second layer 4b, conductive or no, which can be used as an etching or implantation masking layer.
  • the conductive layer 4a can be deposited by low pressure chemical vapor deposition or by epitaxy.
  • An etching step makes it possible to delimit the conductive layer 4 laterally, by means of a mask (not shown), so as to form the gate electrode 5.
  • the deposition of an insulating material on the sides of the gate electrode 5 makes it possible to constitute a lateral insulator 6 of the gate electrode 5.
  • the lateral electrical insulator 6 can be produced by deposition, around the gate electrode 5, a layer having a thickness corresponding to the thickness of the conductive layer 4, followed by etching by means of a mask (not shown).
  • FIG. 2 is shown the etching of the gate insulating layer 3 in the areas of the substrate 2 not covered by the gate electrode 5 and the insulator 6. This etching can be carried out using chlorinated mixtures and a technique of hot cathode type.
  • the etching of the layer 1 of diamond carbon makes it possible to delimit the channel 7 laterally. To attack the diamond carbon, it is sufficient to oxidize it.
  • a mixture of oxygen and argon can be used, serving as a carrier gas and making it possible to dilute the oxygen with a view to finely regulating the attack speed.
  • Layer 1 of diamond carbon can be etched by anisotropic or isotropic etching, as shown in FIG. 3. By isotropic etching, we obtain a shrinkage 8 of layer 1 of diamond carbon under the insulating grid layer 3, preferably up to the gate electrode 5.
  • the isotropic etching can be carried out by low energy oxygen plasma or by means of an oxygen flow directed onto the layer 1 of diamond carbon.
  • Anisotropic etching can be carried out by reactive ion etching using an oxygen plasma.
  • the substrate 2 can be densified by oxygen plasma at the end of the etching of the diamond carbon layer 1.
  • FIG. 4 shows the deposition on the substrate 2, on either side of the channel 7, for example by epitaxy, of a semiconductor material 9a and 9b intended to constitute the source and the drain respectively.
  • An anisotropic etching of the semiconductor material 9a and 9b in the areas of the substrate 2 not covered by the gate electrode and the lateral insulator 6 makes it possible to delimit the semiconductor material 9a and 9b laterally and to form the source 10 and the drain 11, as shown in FIG. 5.
  • the etching of the semiconductor material makes it possible in particular to obtain a small transistor.
  • the fabrication of the transistor ends with the formation of contact elements connected to the source 10 and to the drain 11, by depositing a metal 12 on the substrate 2, planarization, for example by chemical-mechanical route, and etching of the metal. 12.
  • the source 10 and the drain 11 can be made of different materials.
  • the materials 9a and 9b can then be anisotropically etched to delimit the source 10 and the drain 11 respectively, as previously.
  • the semiconductor material 9a can, for example, be diamond, constituting the source 10 of an NMOS or PMOS type transistor.
  • the semiconductor material 9b can, for example, be diamond, germanium, gallium arsenide or indium antimonide to constitute the drain 11 of an NMOS transistor, and diamond or germanium to constitute the drain 11 of a PMOS transistor.
  • the method described above makes it possible in particular to automatically align the source and the drain with respect to the grid. This avoids the formation of parasitic capacitances between drain and gate and between source and gate, which deteriorate the performances of the transistor.
  • the assembly constituted by the gate electrode 5, the lateral insulator 6 and the corresponding part of the gate insulator 3, serves as a mask for etching the layer 1 of diamond carbon, so as to delimit the channel 7. Then , the source and the drain are positioned around the channel, at the same level, under said assembly.
  • a PMOS transistor 13 and an NMOS transistor 14, constituting a CMOS type inverter, respectively comprise a source 10, a drain 11 and a gate electrode.
  • Their gate electrodes 5 are connected to a common conductor 15.
  • the PMOS and NMOS transistors have substantially the same dimensions, in particular their channel widths L are identical.

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention concerns a field-effect transistor comprising a source (10) and a drain (11) connected via a channel (7) controlled by a gate electrode (5) separated from the channel (7) by an gate insulator (3). The channel (7) is made of a diamond-like carbon layer. The method for making the transistor comprises successively: depositing a diamond-like carbon layer on a substrate (2), depositing a gate insulating layer (3) and depositing at least one conductive layer (4). The conductive layer (4) is etched so as to form the gate electrode (5). Then an insulating material is deposited on flanks of the gate electrode (5) to form an insulating side (6). The gate insulating layer (3) is etched and the diamond-like carbon layer is etched so as to define the channel (7). Then, a semiconductor material designed to form the source (10) and a semiconductor material designed to form the drain (11) are deposited on either side of the channel (7).

Description

Procédé de réalisation d'un transistor à effet de champ à canal en carbone diamant et transistor obtenu Method for making a diamond carbon channel field effect transistor and transistor obtained

Domaine technique de l'inventionTechnical field of the invention

L'invention concerne un procédé de réalisation d'un transistor à effet de champ comportant une source et un drain reliés par un canal commandé par une électrode de grille séparée du canal par un isolant de grille, le canal étant constitué par une couche en carbone diamant.The invention relates to a method for producing a field effect transistor comprising a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator, the channel being constituted by a carbon layer. diamond.

État de la techniqueState of the art

Un transistor à effet de champ comporte une source et un drain qui sont reliés par un canal. Une électrode de grille, séparée du canal par un isolant de grille, permet de commander l'état de conduction du canal. Classiquement, la source, le drain et le canal des transistors à effet de champ sont réalisés à partir de matériau semi-conducteur, par exemple le silicium.A field effect transistor has a source and a drain which are connected by a channel. A gate electrode, separated from the channel by a gate insulator, makes it possible to control the conduction state of the channel. Conventionally, the source, the drain and the channel of the field effect transistors are made from semiconductor material, for example silicon.

Pour la réalisation d'un inverseur de type CMOS, un transistor de type PMOS et un transistor de type NMOS sont assemblés. Le fonctionnement optimal de l'inverseur requiert que le courant de saturation dans le transistor PMOS soit égal au courant de saturation dans le transistor NMOS. Dans un transistor NMOS, le courant électrique parcourant le canal est un courant d'électrons, tandis que dans un transistor PMOS, le courant électrique parcourant le canal est un courant de trous. Le courant est proportionnel à la mobilité des porteurs de charge correspondants. La mobilité des électrons dans le silicium étant supérieure à la mobilité des trous dans le silicium, les dimensions des transistors NMOS et PMOS sont adaptées de manière à obtenir des courants de saturation égaux dans les transistors NMOS et PMOS. Ainsi, le transistor PMOS d'un inverseur CMOS, par exemple, a une largeur de canal supérieure à la largeur de canal du transistor NMOS associé. La miniaturisation de l'inverseur CMOS est alors limitée par les dimensions du transistor PMOS.For the production of a CMOS type inverter, a PMOS type transistor and an NMOS type transistor are assembled. Optimal operation of the inverter requires that the saturation current in the PMOS transistor be equal to the saturation current in the NMOS transistor. In an NMOS transistor, the electric current flowing through the channel is an electron current, while in a PMOS transistor, the electric current flowing through the channel is a hole current. The current is proportional to the mobility of the corresponding charge carriers. Since the mobility of electrons in silicon is greater than the mobility of holes in silicon, the dimensions of the NMOS and PMOS transistors are adapted so as to obtain equal saturation currents in the NMOS and PMOS transistors. Thus, the PMOS transistor of a CMOS inverter, for example, has a channel width greater than the channel width of the associated NMOS transistor. The miniaturization of the CMOS inverter is then limited by the dimensions of the PMOS transistor.

Les transistors à effet de champ comportant des canaux en diamant sont bien connus. Le document US5107315, par exemple, décrit un transistor à effet de champ de type métal/isolant/semi-conducteur (MIS) disposé sur une couche isolante en diamant formée sur un substrat en silicium. Une couche de diamant semi-conductrice dopée P forme un canal. Une source et un drain sont formés par des couches en diamant semi-conductrices dopées N. Un isolant de grille en diamant est disposé sur le canal et une électrode de grille est disposée sur cet isolant de grille. Le document US5107315 décrit également un transistor ayant un canal dopé N et des source et drain dopés P. La fabrication du transistor consiste à réaliser successivement le canal, les source et drain, l'isolant de grille et la grille. Un tel transistor peut présenter des capacités parasites entre drain et grille et entre source et grille, ce qui détériore les performances du transistor.Field effect transistors having diamond channels are well known. The document US Pat. No. 5,107,315, for example, describes a metal / insulator / semiconductor (MIS) type field effect transistor arranged on an insulating diamond layer formed on a silicon substrate. A P-doped semiconductor diamond layer forms a channel. A source and a drain are formed by N-doped semiconductor diamond layers. A diamond gate insulator is placed on the channel and a gate electrode is placed on this gate insulator. The document US Pat. No. 5,107,315 also describes a transistor having an N-doped channel and P-doped source and drain. The fabrication of the transistor consists in successively making the channel, the source and drain, the gate insulator and the gate. Such a transistor may have parasitic capacitances between drain and gate and between source and gate, which deteriorates the performance of the transistor.

Objet de l'inventionSubject of the invention

L'invention a pour but de remédier à ces inconvénients et en particulier de permettre de réaliser des transistors et des portes logiques de faibles dimensions présentant de faibles capacités parasites.The object of the invention is to remedy these drawbacks and in particular to make it possible to produce transistors and logic gates of small dimensions having low parasitic capacities.

Selon l'invention, ce but est atteint par les revendications annexées et, en particulier, par le fait que le procédé comporte successivement le dépôt d'une couche de carbone diamant sur un substrat, le dépôt d'une couche isolante de grille sur la couche de carbone diamant, le dépôt, sur la couche isolante de grille, d'au moins une couche conductrice et sa gravure, de manière à former l'électrode de grille, le dépôt d'un matériau isolant sur des flancs de l'électrode de grille pour constituer un isolant latéral, la gravure de la couche isolante de grille, la gravure de la couche de carbone diamant de manière à délimiter le canal, le dépôt, de part et d'autre du canal, d'un matériau semi-conducteur destiné à constituer la source et d'un matériau semi-conducteur destiné à constituer le drain.According to the invention, this object is achieved by the appended claims and, in particular, by the fact that the method successively comprises the deposition of a layer of diamond carbon on a substrate, depositing a gate insulating layer on the diamond carbon layer, depositing, on the gate insulating layer, at least one conductive layer and its etching, so as to form the gate electrode, depositing 'an insulating material on the sides of the gate electrode to constitute a lateral insulator, the etching of the insulating gate layer, the etching of the diamond carbon layer so as to delimit the channel, the deposition, on both sides and 'other of the channel, a semiconductor material intended to constitute the source and a semiconductor material intended to constitute the drain.

L'invention a également pour but un transistor obtenu par le procédé selon l'invention et une porte logique de type CMOS comportant de tels transistors.Another object of the invention is a transistor obtained by the method according to the invention and a CMOS type logic gate comprising such transistors.

Description sommaire des dessinsBrief description of the drawings

D'autres avantages et caractéristiques ressortirόnt plus clairement de la description qui va suivre de modes particuliers de réalisation de l'invention donnés à titre d'exemples non limitatifs et représentés aux dessins annexés, dans lesquels :Other advantages and characteristics appear more clearly from the description which follows of particular embodiments of the invention given by way of nonlimiting examples and represented in the appended drawings, in which:

Les figures 1 à 5 illustrent un mode de réalisation particulier d'un procédé de réalisation d'un transistor selon l'invention. La figure 6 représente schématiquement un inverseur CMOS comportant des transistors selon l'invention. Description de modes particuliers de réalisationFigures 1 to 5 illustrate a particular embodiment of a method for producing a transistor according to the invention. FIG. 6 schematically represents a CMOS inverter comprising transistors according to the invention. Description of particular embodiments

Le transistor à effet de champ selon l'invention comporte un canal constitué par une couche en carbone diamant. Le canal peur être dopé par des dopants du type N pour former un transistor de type PMOS ou des dopants du type P pour former un transistor de type NMOS. Pour un dopage de 1015 atomes par centimètre cube, le carbone diamant a, à température ambiante, une mobilité d'électrons de 1800cm2/Vs et une mobilité de trous de 1800cm2/Vs. Deux transistors, respectivement de type NMOS et de type PMOS, dont les canaux ont des largeurs égales, ont alors des courants de saturation identiques. Ceci permet de construire des portes logiques, par exemple un inverseur CMOS, comportant des transistors de type PMOS et NMOS ayant les mêmes dimensions et dont la surface est 28% inférieure à la surface d'un inverseur CMOS à base de silicium.The field effect transistor according to the invention comprises a channel formed by a diamond carbon layer. The channel can be doped with N type dopants to form a PMOS type transistor or P type dopants to form an NMOS type transistor. For a doping of 10 15 atoms per cubic centimeter, diamond carbon has, at room temperature, an electron mobility of 1800cm 2 / Vs and a hole mobility of 1800cm 2 / Vs. Two transistors, respectively of the NMOS type and of the PMOS type, the channels of which have equal widths, then have identical saturation currents. This makes it possible to build logic gates, for example a CMOS inverter, comprising PMOS and NMOS type transistors having the same dimensions and whose surface is 28% smaller than the surface of a silicon-based CMOS inverter.

Selon l'invention, une couche 1 de carbone diamant est déposée sur un substrat 2, comme représenté à la figure 1. Le substrat peut comporter, à sa surface, une couche mince isolante, par exemple une couche en oxyde ayant une forte constante diélectrique, par exemple de l'alumine. Puis, on dépose une couche isolante de grille 3 sur la couche 1 en carbone diamant. Ensuite, une couche conductrice 4 est déposée sur la couche isolante de grille 3. Comme représenté à la figure 1 , la couche conductrice 4 peut être constituée par la superposition d'une première couche 4a conductrice et d'une seconde couche 4b, conductrice ou non, qui peut être utilisée comme couche de masquage à la gravure ou à l'implantation. La couche 4a conductrice peut être déposée par dépôt chimique en phase gazeuse basse pression ou par épitaxie. Une étape de gravure permet de délimiter la couche conductrice 4 latéralement, par l'intermédiaire d'un masque (non-représenté), de manière à former l'électrode de grille 5. Ensuite, le dépôt d'un matériau isolant sur les flancs de l'électrode de grille 5 permet de constituer un isolant latéral 6 de l'électrode de grille 5. L'isolant électrique latéral 6 peut être réalisé par dépôt, autour de l'électrode de grille 5, d'une couche ayant une épaisseur correspondant à l'épaisseur de la couche conductrice 4, suivi par une gravure par l'intermédiaire d'un masque (non-représenté).According to the invention, a layer 1 of diamond carbon is deposited on a substrate 2, as shown in FIG. 1. The substrate may comprise, on its surface, a thin insulating layer, for example an oxide layer having a high dielectric constant , for example alumina. Then, an insulating grid layer 3 is deposited on the diamond carbon layer 1. Then, a conductive layer 4 is deposited on the insulating grid layer 3. As shown in FIG. 1, the conductive layer 4 can be constituted by the superposition of a first conductive layer 4a and a second layer 4b, conductive or no, which can be used as an etching or implantation masking layer. The conductive layer 4a can be deposited by low pressure chemical vapor deposition or by epitaxy. An etching step makes it possible to delimit the conductive layer 4 laterally, by means of a mask (not shown), so as to form the gate electrode 5. Next, the deposition of an insulating material on the sides of the gate electrode 5 makes it possible to constitute a lateral insulator 6 of the gate electrode 5. The lateral electrical insulator 6 can be produced by deposition, around the gate electrode 5, a layer having a thickness corresponding to the thickness of the conductive layer 4, followed by etching by means of a mask (not shown).

Sur la figure 2 est représentée la gravure de la couche isolante de grille 3 dans les zones du substrat 2 non recouvertes par l'électrode de grille 5 et l'isolant 6. Cette gravure peut être réalisée en utilisant des mélanges chlorés et une technique de type cathode chaude.In FIG. 2 is shown the etching of the gate insulating layer 3 in the areas of the substrate 2 not covered by the gate electrode 5 and the insulator 6. This etching can be carried out using chlorinated mixtures and a technique of hot cathode type.

La gravure de la couche 1 de carbone diamant, représentée à la figure 3, permet de délimiter latéralement le canal 7. Pour attaquer le carbone diamant il suffit de l'oxyder. On favorise la réaction 2C+02=2CO ou encore C+02=C02. On peut utiliser un mélange d'oxygène et d'argon, servant de gaz porteur et permettant de diluer l'oxygène en vue de régler finement la vitesse d'attaque. La couche 1 de carbone diamant peut être gravée par gravure anisotrope ou isotrope, comme représenté à la figure 3. Par gravure isotrope, on obtient un retrait 8 de la couche 1 de carbone diamant sous la couche isolante de grille 3, de préférence jusque sous l'électrode de grille 5. La gravure isotrope peut être effectuée par plasma d'oxygène à faible énergie ou par l'intermédiaire d'un flux d'oxygène dirigé sur la couche 1 de carbone diamant. La gravure anisotrope peut être effectuée par gravure ionique réactive en utilisant un plasma d'oxygène. Le substrat 2 peut être densifié par plasma d'oxygène en fin de la gravure de la couche 1 de carbone diamant.The etching of the layer 1 of diamond carbon, shown in FIG. 3, makes it possible to delimit the channel 7 laterally. To attack the diamond carbon, it is sufficient to oxidize it. The reaction 2C + 0 2 = 2CO or C + 0 2 = C0 2 is favored. A mixture of oxygen and argon can be used, serving as a carrier gas and making it possible to dilute the oxygen with a view to finely regulating the attack speed. Layer 1 of diamond carbon can be etched by anisotropic or isotropic etching, as shown in FIG. 3. By isotropic etching, we obtain a shrinkage 8 of layer 1 of diamond carbon under the insulating grid layer 3, preferably up to the gate electrode 5. The isotropic etching can be carried out by low energy oxygen plasma or by means of an oxygen flow directed onto the layer 1 of diamond carbon. Anisotropic etching can be carried out by reactive ion etching using an oxygen plasma. The substrate 2 can be densified by oxygen plasma at the end of the etching of the diamond carbon layer 1.

Sur la figure 4 est représenté le dépôt sur le substrat 2, de part et d'autre du canal 7, par exemple par épitaxie, d'un matériau semi-conducteur 9a et 9b destiné à constituer respectivement la source et le drain. Une gravure anisotrope du matériau semi-conducteur 9a et 9b dans les zones du substrat 2 non recouvertes par l'électrode de grille et l'isolant latéral 6 permet de délimiter latéralement le matériau semi-conducteur 9a et 9b et de former la source 10 et le drain 11, comme représenté à la figure 5. La gravure du matériau semi-conducteur permet en particulier d'obtenir un transistor de faible taille. La fabrication du transistor se termine par la formation d'éléments de contact reliés à la source 10 et au drain 11 , par dépôt d'un métal 12 sur le substrat 2, planarisation, par exemple par voie mécano-chimique, et gravure du métal 12.FIG. 4 shows the deposition on the substrate 2, on either side of the channel 7, for example by epitaxy, of a semiconductor material 9a and 9b intended to constitute the source and the drain respectively. An anisotropic etching of the semiconductor material 9a and 9b in the areas of the substrate 2 not covered by the gate electrode and the lateral insulator 6 makes it possible to delimit the semiconductor material 9a and 9b laterally and to form the source 10 and the drain 11, as shown in FIG. 5. The etching of the semiconductor material makes it possible in particular to obtain a small transistor. The fabrication of the transistor ends with the formation of contact elements connected to the source 10 and to the drain 11, by depositing a metal 12 on the substrate 2, planarization, for example by chemical-mechanical route, and etching of the metal. 12.

En variante, la source 10 et le drain 11 peuvent être constitués de matériaux différents. Dans ce cas, on peut, par exemple, procéder à un masquage de la zone correspondant au drain 11 pendant le dépôt du matériau semi-conducteur 9a destiné à constituer la source 10, retirer le masque, puis masquer le matériau semi-conducteur 9a pendant le dépôt du matériau semi-conducteur 9b et retirer ce second masque. On peut ensuite graver de façon anisotrope les matériaux 9a et 9b pour délimiter respectivement la source 10 et le drain 11 , comme précédemment.As a variant, the source 10 and the drain 11 can be made of different materials. In this case, it is possible, for example, to mask the area corresponding to the drain 11 during the deposition of the semiconductor material 9a intended to constitute the source 10, remove the mask, then mask the semiconductor material 9a for depositing the semiconductor material 9b and removing this second mask. The materials 9a and 9b can then be anisotropically etched to delimit the source 10 and the drain 11 respectively, as previously.

Le matériau semi-conducteur 9a peut, par exemple, être du diamant, constituant la source 10 d'un transistor de type NMOS ou PMOS. Le matériau semiconducteur 9b peut, par exemple, être du diamant, du germanium, de l'arséniure de gallium ou de l'antimoniure d'indium pour constituer le drain 11 d'un transistor NMOS, et du diamant ou du germanium pour constituer le drain 11 d'un transistor PMOS.The semiconductor material 9a can, for example, be diamond, constituting the source 10 of an NMOS or PMOS type transistor. The semiconductor material 9b can, for example, be diamond, germanium, gallium arsenide or indium antimonide to constitute the drain 11 of an NMOS transistor, and diamond or germanium to constitute the drain 11 of a PMOS transistor.

Le procédé décrit ci-dessus permet notamment d'aligner automatiquement la source et le drain par rapport à la grille. Ceci permet d'éviter la formation de capacités parasites entre drain et grille et entre source et grille, qui détériorent les performances du transistor. En effet, contrairement au procédé de réalisation selon le document US5107315, dans lequel la source et le drain sont réalisés avant la réalisation de la grille, ces étapes sont inversées dans le procédé décrit ci-dessus. L'ensemble constitué par l'électrode de grille 5, l'isolant latéral 6 et la partie correspondante de l'isolant de grille 3, sert de masque pour graver la couche 1 de carbone diamant, de manière à délimiter le canal 7. Puis, la source et le drain se positionnent autour du canal, au même niveau, sous ledit ensemble.The method described above makes it possible in particular to automatically align the source and the drain with respect to the grid. This avoids the formation of parasitic capacitances between drain and gate and between source and gate, which deteriorate the performances of the transistor. In fact, unlike the production method according to document US Pat. No. 5,107,315, in which the source and the drain are produced before the grid is produced, these steps are reversed in the method described above. The assembly constituted by the gate electrode 5, the lateral insulator 6 and the corresponding part of the gate insulator 3, serves as a mask for etching the layer 1 of diamond carbon, so as to delimit the channel 7. Then , the source and the drain are positioned around the channel, at the same level, under said assembly.

Sur la figure 6, un transistor PMOS 13 et un transistor NMOS 14, constituant un inverseur de type CMOS, comportent respectivement une source 10, un drain 11 et une électrode de grille. Leurs électrodes de grille 5 sont reliées à un conducteur commun 15. Les transistors PMOS et NMOS ont sensiblement les mêmes dimensions, en particulier leurs largeurs L de canal sont identiques. In FIG. 6, a PMOS transistor 13 and an NMOS transistor 14, constituting a CMOS type inverter, respectively comprise a source 10, a drain 11 and a gate electrode. Their gate electrodes 5 are connected to a common conductor 15. The PMOS and NMOS transistors have substantially the same dimensions, in particular their channel widths L are identical.

Claims

Revendications claims 1. Procédé de réalisation d'un transistor à effet de champ comportant une source (10) et un drain (11) reliés par un canal (7) commandé par une électrode de grille (5) séparée du canal (7) par un isolant de grille (3), le canal (7) étant constitué par une couche (1) en carbone diamant, procédé caractérisé en ce qu'il comporte successivement le dépôt d'une couche (1 ) de carbone diamant sur un substrat (2), le dépôt d'une couche isolante de grille (3) sur la couche (1) de carbone diamant, le dépôt, sur la couche isolante de grille (3), d'au moins une couche conductrice (4) et sa gravure, de manière à former l'électrode de grille (5), le dépôt d'un matériau isolant sur des flancs de l'électrode de grille (5) pour constituer un isolant latéral (6), - la gravure de la couche isolante de grille (3), la gravure de la couche (1) de carbone diamant de manière à délimiter le canal (7), le dépôt, de part et d'autre du canal (7), d'un matériau semi-conducteur (9a) destiné à constituer la source (10) et d'un matériau semi-conducteur (9b) destiné à constituer le drain (11 ).1. Method for producing a field effect transistor comprising a source (10) and a drain (11) connected by a channel (7) controlled by a gate electrode (5) separated from the channel (7) by an insulator grid (3), the channel (7) consisting of a layer (1) of diamond carbon, method characterized in that it successively comprises the deposition of a layer (1) of diamond carbon on a substrate (2) , depositing a grid insulating layer (3) on the diamond carbon layer (1), depositing, on the grid insulating layer (3), at least one conductive layer (4) and its etching, so as to form the gate electrode (5), the deposition of an insulating material on the sides of the gate electrode (5) to form a lateral insulator (6), - the etching of the gate insulating layer (3), the etching of the layer (1) of diamond carbon so as to delimit the channel (7), the deposition, on either side of the channel (7), of a semiconductor material (9 a) intended to constitute the source (10) and of a semiconductor material (9b) intended to constitute the drain (11). 2. Procédé selon la revendication 1 , caractérisé en ce que la gravure de la couche (1) de carbone diamant est isotrope, de manière à obtenir un retrait de la couche (1) de carbone diamant sous la couche isolante de grille (3).2. Method according to claim 1, characterized in that the etching of the layer (1) of diamond carbon is isotropic, so as to obtain a shrinkage of the layer (1) of diamond carbon under the insulating grid layer (3) . 3. Procédé selon la revendications 2, caractérisé en ce qu'il comporte une gravure anisotrope des matériaux semi-conducteurs (9a, 9b) dans les zones du substrat (2) non recouvertes par l'électrode de grille (5) et l'isolant latéral (6). 3. Method according to claim 2, characterized in that it comprises an anisotropic etching of the semiconductor materials (9a, 9b) in the areas of the substrate (2) not covered by the gate electrode (5) and the lateral insulator (6). 4. Transistor à effet de champ comportant un canal (7) constitué par une couche (1) en carbone diamant, transistor caractérisé en ce qu'il est obtenu par un procédé selon l'une quelconque des revendications 1 à 3.4. Field effect transistor comprising a channel (7) constituted by a layer (1) of diamond carbon, transistor characterized in that it is obtained by a process according to any one of claims 1 to 3. 5. Transistor selon la revendication 4, caractérisé en ce que le canal (7) comporte des dopants du type N, de manière à former un transistor (13) de type PMOS .5. Transistor according to claim 4, characterized in that the channel (7) comprises dopants of the N type, so as to form a transistor (13) of the PMOS type. 6. Transistor selon la revendication 4, caractérisé en ce que le canal (7) comporte des dopants du type P, de manière à former un transistor (14) de type6. Transistor according to claim 4, characterized in that the channel (7) comprises P-type dopants, so as to form a transistor (14) of the type NMOS.NMOS. 7. Porte logique de type CMOS, caractérisée en ce qu'elle comporte des transistors (13, 14) de type PMOS selon la revendication 5 et de type NMOS selon la revendication 6, les transistors PMOS et NMOS ayant sensiblement les mêmes dimensions. 7. CMOS type logic gate, characterized in that it includes PMOS type transistors (13, 14) according to claim 5 and NMOS type transistors according to claim 6, the PMOS and NMOS transistors having substantially the same dimensions.
EP05744607A 2004-03-25 2005-03-25 Method for making a field-effect transistor with diamond-like carbon channel and resulting transistor Withdrawn EP1728269A1 (en)

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FR0403073A FR2868209B1 (en) 2004-03-25 2004-03-25 FIELD-FIELD FIELD EFFECT TRANSISTOR DIAMOND CARBON
PCT/FR2005/000717 WO2005093794A1 (en) 2004-03-25 2005-03-25 Method for making a field-effect transistor with diamond-like carbon channel and resulting transistor

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FR2868209B1 (en) 2006-06-16
WO2005093794A1 (en) 2005-10-06

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