EP1612860B1

EP1612860B1 - Semiconductor device comprising an interposer and manufacturing method thereof

Info

Publication number: EP1612860B1
Application number: EP05253670.3A
Authority: EP
Inventors: Katsuya c/o Shinko Electric Industries Co. LTD Fukase; Shinichi c/o Shinko Electric Industries Co. Ltd. Wakabayashi
Original assignee: Shinko Electric Industries Co Ltd
Current assignee: Shinko Electric Industries Co Ltd
Priority date: 2004-06-30
Filing date: 2005-06-14
Publication date: 2017-06-14
Anticipated expiration: 2025-06-14
Also published as: EP1612860A3; EP1612860A2; US20060001179A1; CN1716587A; JP4343044B2; US20060263937A1; JP2006019368A; US7388293B2; CN1716587B; US7415762B2

Description

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to an interposer for a semiconductor device, more particularly, to an interposer adapted to realize a required fan-out structure between a semiconductor chip to be mounted thereon and a printed wiring board (packaging board) such as a mother board. The present invention also relates to a method of fabricating the interposer, and a semiconductor device using the same.
Such an interposer has a function of mounting a semiconductor chip thereon, and is therefore the same as a wiring board in terms of function and also referred to as a "package."

(b) Description of the Related Art

A typical interposer has a semiconductor chip (typically a silicon (Si) chip) mounted thereon, and is mounted on a printed wiring board to constitute a semiconductor device. As a material constituting the interposer, various materials have been used. One example thereof is silicon (Si). The reason for using Si is that the same material as Si which is a material constituting the semiconductor chip to be mounted thereon is used (i.e., the coefficients of thermal expansion (CTEs) thereof are made approximately equal to each other) to prevent the occurrence of disadvantages such as a warp or a twist due to a difference in thermal shrinkage therebetween.
The interposer in which Si is used as its constituent material has an advantage in that the CTE thereof matches with that of the Si chip to be mounted thereon. In this case, from the viewpoint of CTE matching, it suffices that the size of the Si interposer is approximately the same as the chip size. However, the pitch of external connection terminals to be provided on the opposite surface to the side where the chip is to be mounted is larger than the pitch of terminals of the chip. Accordingly, the size of the interposer becomes larger than the chip size. In particular, where a chip having a large number of terminals is to be mounted, the size of the interposer becomes even larger. Namely, since the interposer is used to match the terminals of the Si chip to be mounted thereon and the terminals (external connection terminals) for connecting with a printed wiring board (i.e., to perform rewiring), the interposer exhibits a form in which an area for the external connection terminals is extended to the periphery of a chip mount area, i.e., a so-called "fan-out structure," from the viewpoint of structure.
Moreover, when such a Si interposer is fabricated in a conventional process, a series of processings (formation of through holes, formation of an insulating layer in the through holes and on the wafer surface, formation of a seed layer or the like on the insulating layer, filling of the through holes with conductors by plating, formation of plated layers on both surfaces and formation of electrical paths between the both surfaces, formation of wiring patterns on the both surfaces, formation of protective films, and the like) are performed on a whole Si wafer, and then the Si wafer is diced into individual pieces (divided into individual pieces), each corresponding to one interposer. Further, external connection terminals are bonded thereto, as needed. Namely, the formation of wiring patterns is performed on the whole Si wafer.
Technologies relating to the above-described conventional technology include, for example, as described in Japanese unexamined Patent Publication (JPP) 2001-326305 , an interposer for a semiconductor device in which a capacitor is provided between wiring patterns directly under a semiconductor chip to be mounted thereon.
As described above, conventional interposers have a "fan-out structure" in which an area occupied by external connection terminals is extended to the periphery of a chip mount area. Accordingly, there has been the following problem: where an interposer is fabricated using only silicon (Si), Si needs to be used even for an area which is essentially unnecessary from the viewpoint of CTE matching with a Si chip to be mounted thereon, i.e., an area extended to the periphery of the chip mount area; consequently, cost is increased.
Moreover, when an interposer is fabricated in a conventional process, processing is performed on the whole Si wafer until the Si wafer is finally divided into individual pieces. Accordingly, there has also been the problem in that it is technically difficult to form wiring patterns having required shapes on both surfaces of the Si wafer. US 6,525,407 discloses an apparatus and method for flexibly bonding an integrated circuit package to a printed circuit board. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first end is configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.
In US 2003/103338 , to accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nano-springs, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described. US 2002/020898 discloses a microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.
WO 2004/047167 discloses a semiconductor device comprising an interposer and a semiconductor chip mounted thereon by flip-chip bonding wherein the interposer is made of material having a thermal expansion coefficient equivalent to that of the semiconductor chip. Wiring patterns on the upper surface and the lower surface of the interposer are electrically connected via through holes.

SUMMARY OF THE INVENTION

Accordingly, it is desirable to provide an interposer which can realize a required fan-out structure and reduce a cost thereof.
It is also desirable to provide an interposer fabrication method by which required wiring patterns can be easily formed on both surfaces of the interposer, and also to provide a semiconductor device constituted using the interposer.
The present invention is defined in independent claims 1, 5 and 6. Particular embodiments of the invention are defined in the dependent claims.
In addition to the advantages obtained by the interposer of the semiconductor device according to the invention, the interposer fabrication method in the semiconductor device fabrication method according to the invention further provides the advantage in that required wiring patterns can be easily formed on both surfaces of an interposer, unlike the case where processing is performed on the whole Si wafer as heretofore, because processing is performed after the first interposer portions have been diced (cut and separated) from the semiconductor wafer and re-laid out on the supporting body.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a cross-sectional view schematically showing the constitution of an interposer (in the case of an extended interposer portion being made of an insulator) according to one embodiment of the present invention;
Fig. 2 is a cross-sectional view schematically showing one example of the constitution of a semiconductor device constituted using the interposer of Fig. 1;
Fig. 3 is a cross-sectional view schematically showing the constitution of a semiconductor device structure constituted using the interposer of Fig. 1;
Fig. 4A is a plan view and Figs.4B to 4D are cross-sectional views, showing one example of steps for fabricating the interposer of Fig. 1;
Fig. 5A is a plan view and Figs.5B to 5D are cross-sectional views, showing fabrication steps subsequent to those of Figs. 4A to 4D;
Figs. 6A to 6C are cross-sectional views showing fabrication steps subsequent to those of Figs. 5A to 5D;
Fig. 7A is a plan view and Figs.7B to 7D are cross-sectional views, showing one example of steps for fabricating an interposer (in the case of the extended interposer portion being made of a metal body) according to another embodiment of the present invention;
Fig. 8A is a plan view and Figs.8B to 8D are cross-sectional views, showing fabrication steps subsequent to those of Figs. 7A to 7D;
Figs. 9A to 9C are cross-sectional views showing fabrication steps subsequent to those of Figs. 8A to 8D;
Fig. 10A is a plan view and Figs.10B to 10D are cross-sectional views, showing another example of steps for fabricating an interposer (in the case of the extended interposer portion being made of a metal body) not forming part of the present invention; and
Figs. 11A to 11D are cross-sectional views showing fabrication steps subsequent to those of Figs. 10A to 10D.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Fig. 1 schematically shows, in a cross-sectional view, the constitution of an interposer according to one embodiment of the present invention. In the illustrated example, in order to clearly show the portions relating to the present invention, the constitution of the interposer is shown in a simplified manner. The detailed constitution (structure) thereof will be described later in conjunction with the process.
On the interposer 10 according to this embodiment, a silicon (Si) chip 1 is mounted as indicated by dashed lines in the drawing. As described later, the interposer 10 with the Si chip 1 mounted thereon is mounted on a packaging board to constitute a semiconductor device. The interposer 10 has, as its basic structure, a portion 11 (hereinafter referred to as a "Si interposer portion") which is made of Si necessary for matching its coefficient of thermal expansion (CTE) with that of the Si chip 1 to be mounted thereon, and a portion 12 (hereinafter referred to as an "extended interposer portion") which is extended to the periphery (around the Si interposer portion 11 in the plane thereof) of a chip mount area in order to realize a required fan-out structure. The Si interposer portion 11 and the extended interposer portion 12 are integrally provided. The Si interposer portion 11 has a size approximately equal to that of the Si chip 1 to be mounted thereon, when viewed two-dimensionally. Further, the extended interposer portion 12 is made of an insulator. In this embodiment, epoxy resin is used in consideration of cost (reduction in cost) and processing (ease of processing).
Moreover, on both surfaces of the Si interposer portion 11, wiring patterns (e.g., plated copper (Cu) layers) 14a and 14b are formed in required shapes with insulating layers 13a and 13b interposed therebetween, respectively. The wiring patterns 14a and 14b are electrically connected to each other via through holes formed at required positions in the Si interposer portion 11. Similarly, on both surfaces of the extended interposer portion 12, wiring patterns 15a and 15b are formed in required shapes, respectively. The wiring patterns 15a and 15b are electrically connected to each other via through holes formed at required positions in the extended interposer portion 12. The through holes formed in the interposer portions 11 and 12 are filled with conductors (e.g., Cu). Alternatively, conductors are formed on the inner walls thereof. Further, although not clearly shown in Fig. 1, the wiring patterns 14a and 14b of the Si interposer portion 11 and the wiring patterns 15a and 15b of the extended interposer portion 12 are connected to each other at required positions.
Each of the wiring patterns 14a, 14b, 15a, and 15b is formed to include pad portions at required positions. In the constitution according to this embodiment, the wiring patterns 14a and 15a on the side where the Si chip 1 is to be mounted are formed in such a manner that pad portions are delimited at positions corresponding to the positions of electrode terminals 2 (e.g., solder bumps or gold (Au) stud bumps) of the Si chip 1 to be mounted, and the wiring patterns 14b and 15b on the opposite side are formed in such a manner that pad portions are delimited at positions corresponding to the bonding positions of external connection terminals 16 (e.g., solder bumps) which are to be used when the interposer 10 is mounted on a packaging board. In the illustrated example, the structure is shown in which one layer of wiring patterns 14a and 14b (15a and 15b) is formed on each surface of the interposer portion 11 (12). However, it is a matter of course that the number of wiring layers may be further increased by a build-up process or the like, as needed.
Moreover, although not clearly shown in Fig. 1, protective films (e.g., solder resist layers) are formed on both surfaces of the interposer portions 11 and 12 so as to cover the entire surface in such a manner that the pad portions of the wiring patterns 14a, 14b, 15a, and 15b are exposed. Furthermore, on the wiring patterns (pad portions) exposed from the protective films, plated layers of nickel (Ni)/gold (Au) are deposited. Incidentally, in the illustrated example, the external connection terminals 16 are provided, but these terminals do not necessarily need to be provided. It suffices that the pad portions (plated Ni/Au layers) are exposed from the protective films so that external connection terminals can be bonded thereto when necessary.
The interposer 10 according to this embodiment basically has the following features: there are integrally provided the Si interposer portion 11 having the size necessary for matching its CTE with that of the Si chip 1 to be mounted thereon, and the extended interposer portion 12 necessary to realize a required fan-out structure; and multilayer stacking can be realized using the pad portions exposed from the protective films or the external connection terminals bonded to the pad portions, as needed as described later.
In this embodiment, the interposer portion 11 made of Si is provided as a component for performing CTE matching with the Si chip 1. However, it is a matter of course that the material of the interposer portion 11 is not limited to Si as long as it is a material having a CTE equivalent to that of the Si chip 1. For example, low firing temperature ceramic such as glass ceramic can be suitably used.
Fig. 2 schematically shows one example of the constitution of a semiconductor device constituted using the interposer 10 according to the above-described embodiment.
The illustrated semiconductor device 50 is constituted by mounting the interposer 10 with the Si chip 1 mounted thereon on a printed wiring board (packaging board) 51 such as a mother board. When the Si chip 1 is mounted on the interposer 10, for example, the flip-chip bonding of the chip is performed in such a manner that the electrode terminals 2, such as solder bumps, which are bonded to the pads of the Si chip 1 are electrically connected to the pad portions of the wiring pattern which are exposed from the solder resist layer (protective film) on the upper side, and furthermore, underfill resin (e.g., epoxy resin) is filled into the space between the chip and the solder resist layer, and cured, whereby the Si chip 1 is bonded to the interposer 10. In this case, the flip-chip bonding and the filling of the underfill resin can also be simultaneously performed. Further, when the interposer 10 is mounted on the printed wiring board 51, in a similar way, solder balls to serve as external connection terminals (solder bumps 16) are bonded by reflow to the pad portions of the wiring patterns which are exposed from the solder resist layer (protective film) on the lower side, and the pad portions are connected via the solder bumps 16 to corresponding pads or lands 52 on the printed wiring board 51.
Fig. 3 schematically shows the constitution of a semiconductor device structure 50a constituted using semiconductor devices 50 according to the above-described embodiment. In the illustrated semiconductor device structure 50a a plurality of interposers 10 (two interposers in the illustrated example) with Si chips 1 mounted thereon are electrically connected to each other and stacked in a multilayered manner. In this case, the electrical connection between the interposers 10 is established via the pad portions (on the upper side) of the lower interposer 10 and the external connection terminals 16 bonded to the pad portions (on the lower side) of the upper interposer 10. Note that the printed wiring board (packaging board) 51 shown in Fig. 2 is not shown in the example shown in Fig. 3.
Moreover, although not particularly shown in the drawing, in consideration of adaptability to a multi-chip module, a semiconductor device can also be constituted in the constitution in which a plurality of interposers 10 according to this embodiment are two-dimensionally arranged.
Next, a method of fabricating the interposer 10 according to this embodiment will be described with reference to Figs. 4A to 6C showing one example of a fabricating process thereof. In the cross-sectional constitutions shown in Figs. 4A to 6C, for simplification of illustration, only (part of) the Si interposer portion 11 and (part of) the extended interposer portion 12 adjacent thereto are shown.
To begin with, in the first step (Fig. 4A), a Si wafer having a size of, for example, 12 inches, is prepared and thinned to a predetermined thickness (approximately 50 to 300 µm). Then, through holes TH1 are formed at required positions in this Si wafer 20 by dry etching, such as reactive ion etching (RIE) or sputter etching.
In the next step (Fig. 4B), an insulating layer 21 of SiO₂ (silicon oxide film) is formed on the entire surface including the inner walls of the through holes TH1, for example, by CVD or thermal oxidation.
In the next step (Fig. 4C), a seed layer 22 of copper (Cu) is formed on the entire surface of the insulating layer 21, for example, by electroless plating, sputtering, or vapor deposition.
In the next step (Fig. 4D), the through holes TH1 are filled with conductors, and wiring patterns 23 are formed in required shapes on both surfaces to be connected to the conductors. For example, using the seed layer 22 as a power-supplying layer, the through holes TH1 are filled by electrolytic Cu plating. Alternatively, conductive paste containing metal such as Cu is filled into the through holes TH1 by screen printing, inkjet printing, or the like. Further, the Cu wiring patterns 23 having required shapes are formed on the filled conductors by a subtractive process, a semi-additive process, inkjet printing, or the like. Where a semi-additive process or inkjet printing is used, the wiring patterns 23 can be formed simultaneously with the filling of the through holes TH1 with conductors (Cu). This contributes to a simplification of the process.
The wiring patterns 23 formed here correspond to the wiring patterns 14a and 14b shown in Fig. 1. In the illustrated example, there are formed two layers of wiring patterns 23 in total, one layer on each surface (on the insulating layer 21) of the Si wafer 20. However, it is a matter of course that the number of layers of wiring patterns to be formed is not limited to two. The number of layers of wiring may be appropriately increased by a build-up process or the like, as needed.
In the next step (Fig. 5A), the Si wafer 20 with the wiring patterns 23 formed on both surfaces thereof is cut into individual shapes (in this embodiment, the shapes of Si chips 1 to be mounted) of Si interposer portions 11 as seen two-dimensionally, for example, using a dicer, to be divided into individual pieces, each corresponding to one interposer.
In the next step (Fig. 5B), a supporting body 24 is prepared in which an insulating film 25 made of epoxy resin, polyimide resin, or the like, is formed on one surface thereof. On the insulating film 25 of the supporting body 24, the Si interposer portions 11 (each of which is part of the interposer 10) which have been obtained as individual pieces in the preceding step are arranged at a predetermined regular interval therebetween. The supporting body 24 may be made of a metal body, or may be in the form of a tape member or the like. In the latter case, it is desirable that the surface of the tape member on which the insulating film 25 is to be formed is coated with a release agent. That is because such an agent makes it convenient when the supporting body 24 is stripped off and removed in a later stage.
In the next step (Fig. 5C), resin is filled into the gaps between the Si interposer portions 11 to form a resin layer 26. Further, an insulating film 27 is formed on the Si interposer portions 11 and the resin layer 26 by CVD, lamination, or the like. For example, the resin layer 26 can be formed as follows: a low-viscosity thermosetting epoxy resin is melted and poured into the gaps between the Si interposer portions 11, and directly subjected to hot pressing from above.
Part of the resin layer 26 formed here constitute the extended interposer portions 12 shown in Fig. 1. Further, the insulating films 27 and 25 formed on both surfaces of the Si interposer portions 11 and the resin layer 26 with the Si interposer portions 11 and the resin layer 26 interposed therebetween correspond to the insulating layers 13a and 13b shown in Fig. 1, respectively.
In the next step (Fig. 5D), the supporting body 24 (Fig. 5C) is removed by wet etching (in the case of a metal), stripping-off (in the case of a tape member), or the like.
In the next step (Fig. 6A), through holes TH2 are formed at required positions in the resin layer 26 (including the insulating films 25 and 27), for example, using a mechanical drill, a UV-YAG laser, a CO₂ laser, or an excimer laser. Further, via holes VH are formed on required portions (pad portions) of the wiring patterns 23 of the Si interposer portions 11 so as to reach the pad portions, for example, using a laser.
In the next step (Fig. 6B), a seed layer (Cu) is formed on the entire surfaces of the insulating films 25 and 27 including the insides of the through holes TH2 and the via holes VH by electroless plating, sputtering, or the like. Using the seed layer as a power-supplying layer, the through holes TH2 and the via holes VH are filled by electrolytic Cu plating (alternatively, conductive paste containing metal such as Cu is filled into the through holes TH2 by screen printing, inkjet printing, or the like). Then, Cu wiring patterns 28 having required shapes are formed by a subtractive process, a semi-additive process, inkjet printing, or the like, so as to connect the conductors filled in the through holes TH2 and the pad portions of the wiring patterns 23 which are exposed from the via holes VH.
The wiring patterns 28 formed here correspond to the wiring patterns 15a and 15b shown in Fig. 1.
In the final step (Fig. 6C), solder resist layers 29 are formed to cover the entire surface in such a manner that the pad portions delimited at required positions in the wiring patterns 28 on both surfaces are exposed. Further, the pad portions (Cu) exposed from the solder resist layers 29 are plated with Ni/Au (formation of plated Ni/Au layers 30). This is intended to obtain improved adhesiveness with the pad portions when solder bonding is performed in a later stage. Furthermore, portions of the resin layer 26 (including the insulating films 25 and 27) are cut in such a manner that specified areas for the extended interposer portions 12 (Fig. 1) are delimited, thereby separating pieces, each including one Si interposer portion 11.
By the above-described steps, the interposer 10 according to this embodiment is fabricated. Incidentally, after the plated Ni/Au layers 30 have been formed in the final step, solder bumps to be used as the external connection terminals 16 (Fig. 1) may be formed on the pad portions (one plated Ni/Au layer 30) which are exposed from one solder resist layer 29, as needed.
As described above, according to the interposer 10 (Fig. 1) of this embodiment and the method of fabricating the same, the Si interposer portion 11 has a size approximately equal to that of the Si chip 1 to be mounted thereon. Accordingly, it is possible to match its coefficient of thermal expansion (CTE) matching with that of the Si chip 1. On the other hand, the extended interposer portion 12 provided in an area (i.e., an area which is essentially unnecessary from the viewpoint of CTE matching with the Si chip 1 to be mounted) around the Si interposer portion 11 is made of an insulator (epoxy resin). Accordingly, Si does not need to be used for an unnecessary area as heretofore, and the amount of Si used can be reduced to a required minimum. Thus, cost can be reduced. Further, the presence of the extended interposer portion 12 makes it possible to realize a required fan-out structure.
Moreover, in relation to this, since a stress occurring between the Si chip 1 and the Si interposer portion 11 can be relaxed by CTE matching, flexibility can be improved in selecting the material constituting the extended interposer portion 12.
Moreover, in the fabricating method (Figs. 4A to 6C) according to this embodiment, processing is performed after the Si interposer portions 11 have been cut and separated from the Si wafer 20 and re-laid out on the supporting body 24. Accordingly, unlike the case where processing is performed on the whole Si wafer without cut and separation of the Si interposer portions as heretofore, required wiring patterns can be easily formed on both surfaces of the interposer 10.
Moreover, since the external connection terminals 16 can be bonded to the pad portions of the wiring patterns which are exposed from one solder resist layer (protective film) 29 as needed, a plurality of interposers 10 (with Si chips 1 mounted thereon) can be stacked in a multilayered manner as shown in Fig. 3.
Moreover, even if a stress such as a warp or a twist occurs when the Si wafer is thinned prior to the formation of the through holes TH1 in the step of Fig. 4A, the stress can be removed by dicing to be performed in a later stage (Fig. 5A). Accordingly, the processing becomes easy due to the thin Si wafer. This can contribute to a reduction in the thickness of the interposer 10.
Furthermore, where the formation of through holes is carried out only in the resin area (area of the extended interposer portion 12), a wiring board process can be used for processing the through holes and for forming electrical paths in the through holes. Accordingly, the process can be simplified. This makes it possible to reduce cost and to shorten a procedure.
In the above-described embodiment (Fig. 1), the description has been made by taking as an example the case where the extended interposer portion 12 provided around the Si interposer portion 11 is made of an insulator (epoxy resin). However, it is a matter of course that the material constituting the extended interposer portion 12 is not limited to this. For example, the extended interposer portion 12 can also be made of a metal body instead of an insulator.
Hereinafter, an embodiment for the case where the extended interposer portion is made of a metal body will be described. Incidentally, the constitution of an interposer according to this embodiment is the same as that of the interposer 10 shown in Fig. 1 in terms of the appearance, and therefore will not be further described here.
In addition to the advantages obtained by the above embodiment, the constitution of the interposer (for the case where the extended interposer portion is made of a metal body) according to this embodiment also provides the advantage in that heat generated inside can be dissipated into the outside environment when the interposer is constituted as a semiconductor device, because the extended interposer portion is made of a metal body.
Hereinafter, a method of fabricating the interposer provided with the extended interposer portion made of a metal body will be described with reference to Figs. 7A to 9C showing one example of a fabricating process thereof.
First, of the fabricating process according to the above embodiment, the steps of Figs. 4A to 5A are performed. In the next step (Fig. 7A), through holes TH3 are formed at required positions in a metal plate 40 of aluminum (Al), copper (Cu), or the like, having a predetermined thickness (approximately 50 to 300 µm) by wet etching; a hole-making process using a mechanical drill; laser processing using a UV-YAG laser, a CO₂ laser, an excimer laser, or the like. In doing so, an opening portion for accommodating the Si interposer portion 11 may be simultaneously formed.
In the next step (Fig. 7B), an insulating layer 41 made of epoxy resin, polyimide resin, or the like, is formed on the entire surface including the inner walls of the through holes TH3, for example, by electrophoretic deposition.
In the next step (Fig. 7C), a seed layer 42 of copper (Cu) is formed on the entire surface of the insulating layer 41, for example, by electroless plating, sputtering, or vapor deposition.
In the next step (Fig. 7D), the through holes TH3 are filled with conductors, and wiring patterns 43 having required shapes are formed on both surfaces so as to be connected to these conductors. For example, using the seed layer 42 as a power-supplying layer, the through holes TH3 are filled by electrolytic Cu plating. Alternatively, conductive paste containing metal such as Cu is filled into the through holes TH3 by screen printing, inkjet printing, or the like. Further, Cu wiring patterns 43 having required shapes are formed on the filled conductors by a subtractive process, a semi-additive process, inkjet printing, or the like. Where a semi-additive process or inkjet printing is used, the wiring patterns 43 can be formed simultaneously with the filling of the through holes TH3 with conductors (Cu) (simplification of process).
The wiring patterns 43 formed here correspond to the wiring patterns 15a and 15b shown in Fig. 1. In the illustrated example, there are formed two layers of wiring patterns 43 in total, one layer on each surface (on the insulating layer 41) of the metal plate 40. However, it is a matter of course that the number of layers of wiring patterns to be formed is not limited to two. The number of layers of wiring may be appropriately increased by a build-up process or the like, as needed.
In the next step (Fig. 8A), for example, using a dicer, the metal plate 40 with the wiring patterns 43 formed on both surfaces thereof is cut into the shapes of required extended interposer portions 12a (part of the interposer), i.e., "frame-like" shapes in which an opening portion OP for accommodating the Si interposer portion 11 is formed as shown in the drawing, to be divided into individual pieces, each corresponding to one interposer. Incidentally, the opening portion for accommodating the Si interposer portion 11 is formed by cutting using a dicer or the like in this step. However, before or after cutting using the dicer or the like, the opening portion may be formed by stamping using a press or the like.
In the next step (Fig. 8B), a supporting body 44 is prepared with an insulating film 45 made of epoxy resin, polyimide resin, or the like, formed on one surface thereof. On the insulating film 45 of the supporting body 44, the Si interposer portions 11 already obtained as individual pieces and the extended interposer portions 12a obtained as individual pieces in the preceding step are arranged. In doing so, the Si interposer portion 11 is arranged in such a manner that it is accommodated in the opening portion OP formed in the extended interposer portion 12a. The supporting body 44 may be made of a metal body, or may be in the form of a tape member or the like (here, the surface thereof on which the insulating film 45 is formed is coated with a release agent).
In the next step (Fig. 8C), an insulating film 46 is formed on the entire surface including the spaces between the Si interposer portions 11 and the extended interposer portions 12a and the spaces between adjacent extended interposer portions 12a, by CVD, lamination, or the like. Alternatively, thermosetting resin may be applied to the entire surface and cured to form the insulating film 46.
The insulating film 46 formed here and the insulating film 45 formed in the preceding step correspond to the insulating layers 13a and 13b shown in Fig. 1, respectively.
In the next step (Fig. 8D), the supporting body 44 (Fig. 8C) is removed by wet etching (in the case of a metal), stripping-off (in the case of a tape member), or the like.
In the next step (Fig. 9A), via holes VH1 and VH2 are formed on required portions (pad portions) of the wiring patterns 23 and 43 of the Si interposer portions 11 and the extended interposer portions 12a so as to reach the pad portions, for example, using a UV-YAG laser, a CO₂ laser, or an excimer laser.
In the next step (Fig. 9B), Cu wiring patterns 47 having required shapes are formed by a subtractive process, a semi-additive process, screen printing using conductive paste, or the like, so as to connect the pad portions of the wiring patterns 23 which are exposed from the via holes VH1 formed in the Si interposer portions 11 and the pad portions of the wiring patterns 43 which are exposed from the via holes VH2 formed in the extended interposer portions 12a.
The wiring patterns 47 formed here correspond to the wiring patterns 15a and 15b shown in Fig. 1.
In the final step (Fig. 9C), solder resist layers 29 are formed to cover the entire surface in such a manner that the pad portions delimited at required positions in the wiring patterns 47 on both surfaces are exposed. Further, the pad portions (Cu) exposed from the solder resist layers 29 are plated with Ni/Au (formation of plated Ni/Au layers 30). Furthermore, insulating film portions around the extended interposer portions 12a are cut, thereby separating pieces, in such a manner that one Si interposer portion 11 and the extended interposer portion 12a placed around the Si interposer portion 11 are included in each piece.
By the above-described steps, the interposer 10a according to this embodiment is fabricated. As in the case of the aforementioned embodiment, after the plated Ni/Au layers 30 have been formed in the final step, solder bumps (external connection terminals 16 in Fig. 1) may be formed on the pad portions (one plated Ni/Au layer 30) which are exposed from one solder resist layer 29, as needed.
Next, a method of fabricating an interposer according to an example not forming part of the invention for the case where the extended interposer portion is made of a metal body will be described with reference to Figs. 10A to 11D.
First, the steps of Figs. 4A to 5A are performed. In the next step (Fig. 10A), through holes TH4 are formed at required positions in a metal plate 40 of aluminum (Al), copper (Cu), or the like, having a predetermined thickness (approximately 50 to 300 µm) by wet etching; a hole-making process using a mechanical drill; laser processing using a CO₂ laser, an excimer laser, or the like. Furthermore, the metal plate 40 is cut into the shapes of required extended interposer portions 12b, i.e., "frame-like" shapes in which an opening portion OP for accommodating the Si interposer portion 11 is formed as shown in the drawing, to be divided into individual pieces, each corresponding to one interposer.
In the next step (Fig. 10B), as in the process performed in the step of Fig. 8B, a supporting body 44 is prepared in which an insulating film 45 made of epoxy resin, polyimide resin, or the like, is formed on one surface thereof. On the insulating film 45 of the supporting body 44, the Si interposer portions 11 already obtained as individual pieces and the extended interposer portions 12b obtained as individual pieces in the preceding step are arranged. In doing so, the Si interposer portion 11 is arranged in such a manner that it is accommodated in the opening portion formed in the extended interposer portion 12b. The supporting body 44 may be made of a metal body, or may be in the form of a tape member or the like (here, the surface thereof on which the insulating film 45 is formed is coated with a release agent).
In the next step (Fig. 10C), an insulating film 46 is formed on the entire surface including the spaces between the Si interposer portions 11 and the extended interposer portions 12b and the spaces between adjacent extended interposer portions 12b, by CVD, lamination, or the like. At this time, the insulating film is also formed (filled) in the through holes TH4 formed in the metal plate 40. Incidentally, the insulating film 46 may be formed by applying and curing thermosetting resin. The insulating film 46 formed here and the insulating film 45 formed in the preceding step correspond to the insulating layers 13a and 13b shown in Fig. 1, respectively.
In the next step (Fig. 10D), the supporting body 44 (Fig. 10C) is removed by wet etching (in the case of a metal), stripping-off (in the case of a tape member), or the like.
In the next step (Fig. 11A), through holes TH5 are formed at predetermined positions (positions of the through holes TH4 filled with an insulating film) in the extended interposer portions 12b, for example, using a UV-YAG laser, a CO₂ laser, or an excimer laser. Furthermore, via holes VH3 are formed on required portions (pad portions) of the wiring patterns 23 of the Si interposer portions 11 so as to reach the pad portions, for example, using a laser.
In the next step (Fig. 11B), a seed layer (Cu) is formed on the entire surface including the insides of the through holes TH5 by electroless plating, sputtering, or the like. Using this seed layer as a power-supplying layer, the through holes TH5 are filled by electrolytic Cu plating. Alternatively, conductive paste (conductors 48) containing metal such as Cu is filled into the through holes TH5 by screen printing, inkjet printing, or the like.
In the next step (Fig. 11C), Cu wiring patterns 47 having required shapes are formed by a subtractive process, a semi-additive process, inkjet printing, or the like, so as to connect the conductors 48 filled in the through holes TH5 and the pad portions of the wiring patterns 23 which are exposed from the via holes VH3.
The wiring patterns 47 formed here correspond to the wiring patterns 15a and 15b shown in Fig. 1.
In the final step (Fig. 11D), solder resist layers 29 are formed to cover the entire surface in such a manner that the pad portions delimited at required positions in the wiring patterns 47 on both surfaces are exposed. Further, the pad portions (Cu) exposed from the solder resist layers 29 are plated with Ni/Au (formation of plated Ni/Au layers 30). Furthermore, insulating film portions around the extended interposer portions 12b are cut to be separated into pieces, in such a manner that one Si interposer portion 11 and the extended interposer portion 12b placed around the Si interposer portion 11 are included in each piece.
By the above-described steps, the interposer 10b according to this example is fabricated. As in the aforementioned embodiments, after the plated Ni/Au layers 30 have been formed in the final step, solder bumps (external connection terminals 16 in Fig. 1) may be formed on the pad portions (one plated Ni/Au layer 30) which are exposed from one solder resist layer 29, as needed.

Claims

A semiconductor device which comprises an interposer (10, 10a, 10b) and a semiconductor chip (1) mounted thereon by flip-chip bonding, the interposer (10, 10a, 10b) with the semiconductor chip (1) mounted thereon being suitable for mounting on a packaging board (51), the interposer comprising:
a first interposer portion (11) made of a semiconductor and provided with pad portions in first wiring patterns (14a) and in second wiring patterns (15a) on an upper surface of the first interposer portion (11) electrically connected to electrode terminals (2) of the semiconductor chip (1) and pad portions for external connection terminals (16) in third wiring patterns (14b) on a lower surface of the first interposer portion (11); and

a second interposer portion (12, 12a, 12b) made of an insulator and provided around the first interposer portion integrally with, and in the same plane as, the first interposer portion, the second interposer portion (12, 12a, 12b) being provided with the second wiring patterns (15a), extending on an upper surface of the second interposer portion (12, 12a, 12b) from the first interposer portion (11), and pad portions for external connection terminals (16) in fourth wiring patterns (15b) on a lower surface of the second interposer portion (12, 12a, 12b);
wherein:
(a) a first insulating layer (13a) is formed on the upper surfaces of the first interposer portion (11) and the second interposer portion (12, 12a, 12b), and a second insulating layer (13b) is formed on the lower surfaces of the first interposer portion (11) and the second interposer portion (12, 12a, 12b);

(b) the first and second wiring patterns (14a, 15a) are formed over the first insulating layer (13a), the third and fourth wiring patterns (14b, 15b) are formed over the second insulating layer (13b), and the first and third wiring patterns (14a, 14b) are electrically connected via through holes formed in the first interposer portion (11) and the second and fourth wiring patterns (15a, 15b) are electrically connected via through holes formed in the second interposer portion (12, 12a, 12b);

(c) the first interposer portion (11) has a size approximately equal to that of the semiconductor chip (1) mounted thereon; and

(d) the first interposer portion (11) is made of material having a thermal expansion coefficient equivalent to that of the semiconductor chip (1) mounted thereon.
The semiconductor device according to claim 1, wherein the upper and lower surfaces of the first and second interposer portions (11; 12, 12a, 12b) are covered with protective films (29) in such a manner that the pad portions in the first and second wiring patterns (14a, 15a) are exposed.
The semiconductor device according to claim 2, further comprising external connection terminals (16) bonded to a required number of pad portions among the plurality of pad portions exposed from the protective films.
The semiconductor device according to any preceding claim, wherein the second interposer portion (12) is made of resin.
A semiconductor device structure (50a) wherein a required number of semiconductor devices each according to any one of claims 1 to 4 are stacked and electrically connected to each other.
A method of fabricating a semiconductor device which comprises an interposer (10, 10a, 10b) and a semiconductor chip (1) mounted thereon by flip-chip bonding, which method comprises the steps of:
forming first through holes (TH1) in a semiconductor wafer (20);

forming a wafer insulating layer (21) on the entire surface of the semiconductor wafer, including inner walls of the first through holes, and then forming wafer wiring patterns (23) on each surface of the wafer insulating layer, including insides of the first through holes;

dicing the semiconductor wafer with the wafer wiring patterns formed thereon into individual shapes of first interposer portions (11);

forming second through holes (TH3) in a metal plate (40);

forming a plate insulating layer (41) on the entire surface of the metal plate, including inner walls of the second through holes, and then forming plate wiring patterns (43) on each surface of the plate insulating layer, including insides of the second through holes;

dicing the metal plate with the plate wiring patterns formed thereon into individual shapes of second interposer portions (12a) having respective opening portions (OP);

arranging the diced first interposer portions (11) and the second interposer portions (12a) on a first insulating film (45) formed on one surface of a supporting body (44), in such a manner that each of the first interposer portions is positioned inside respective ones of the opening portions of the second interposer portions so that all the interposer portions are spaced apart from each other;

forming a second insulating film (46) over the entire surface of the first and second interposer portions, including the spaces between the first and second interposer portions and the spaces between adjacent ones of the second interposer portions;

removing the supporting body (44), and then forming through the first and second insulating films (45, 46) first and second via holes (VH1, VH2) to expose portions of the wafer wiring patterns and plate wiring patterns, respectively;

forming additional wiring patterns (47) on the first and second insulating films (45, 46), some of the additional wiring patterns on the second insulating film electrically connecting portions of the wafer wiring patterns and portions of the plate wiring patterns exposed from the first and second via holes;

forming protective films (29) covering the entire surface of the resultant structure in such a manner that pad portions of the additional wiring patterns are exposed, the pad portions exposed in the additional wiring patterns which were formed over the second insulating film and above the first interposer portion being provided for making interconnections to electrode terminals of the semiconductor chip and the pad portions exposed in the additional wiring patterns which were formed on the first insulating film and on the first and second interposer portions being provided for external connection terminals (16);

cutting the first and second insulating films (45, 46) between adjacent ones of the second interposer portions thereby forming separate pieces, wherein each piece constitutes a respective interposer; and

mounting the semiconductor chip on the interposer by flip-chip bonding;
wherein:
(a) the first interposer portion (11) has a size approximately equal to that of the semiconductor chip (1) mounted thereon; and

(b) the first interposer portion (11) is made of material having a thermal expansion coefficient equivalent to that of the semiconductor chip (1) mounted thereon.