EP1464084A1 - Photodiode array and method for establishing a link between a first semiconductor element and a second semiconductor element - Google Patents
Photodiode array and method for establishing a link between a first semiconductor element and a second semiconductor elementInfo
- Publication number
- EP1464084A1 EP1464084A1 EP02704576A EP02704576A EP1464084A1 EP 1464084 A1 EP1464084 A1 EP 1464084A1 EP 02704576 A EP02704576 A EP 02704576A EP 02704576 A EP02704576 A EP 02704576A EP 1464084 A1 EP1464084 A1 EP 1464084A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- photodiode
- submount
- wafer
- metallization
- semiconductor components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 25
- 235000012431 wafers Nutrition 0.000 claims abstract description 70
- 230000005496 eutectics Effects 0.000 claims abstract description 15
- 239000002131 composite material Substances 0.000 claims abstract description 13
- 238000001465 metallisation Methods 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical group [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 description 7
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
- H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/93—Interconnections
- H10F77/933—Interconnections for devices having potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/95—Circuit arrangements
- H10F77/953—Circuit arrangements for devices having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
- H01S5/068—Stabilisation of laser output parameters
- H01S5/0683—Stabilisation of laser output parameters by monitoring the optical output parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
- H01S5/42—Arrays of surface emitting lasers
- H01S5/423—Arrays of surface emitting lasers having a vertical cavity
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
Definitions
- the invention relates to a photodiode arrangement with a photodiode and a submount, via which electrical contact is made with the photodiode, and a method for establishing a connection between a first
- Semiconductor component and a second semiconductor component in particular between a photodiode and a submount for a photodiode, the interconnected semiconductor components having a different outer contour.
- an electro-optical coupling module with a laser diode arrangement in which a plurality of vertically emitting VCSEL laser diodes are arranged in an array.
- the laser diodes are assigned optical fibers arranged in one plane, the end faces of which on the coupling side cause the light emitted by the laser diodes to be deflected into the optical fibers.
- FIG. 7 A corresponding structure known in the prior art is shown schematically in FIG. 7. Thereafter, a laser diode array 101 is arranged on a submount 100, which in the exemplary embodiment shown consists of sixteen VCSEL diodes 102. Twelve of these laser diodes 102 are used for data communications and accordingly a schematically represented optical waveguide 103 is assigned to each of them.
- monitor diode 111, 112 consisting of gallium arsenide is assigned, the optically active surface of which is positioned directly above the outermost laser diode 104, 105 and faces it.
- the optically active surface of the photodiode on the side facing away from the laser diodes 104, 105, that is to say at the top.
- a deflection optics would then be required in order to direct the laser beam onto the optically active surface of the monitor diode.
- the monitor diode 111, 112 is formed in each case in a carrier 113, 114 which is attached to a submount 115, 116 serving as a spacer.
- the submount is a ceramic carrier.
- the contacting of the monitor diodes 111-, 112 and also of the laser diodes 102, 104, 105 takes place via bond wires 117, which are connected via metallizations 118 and further bond wires 119 to contacts of a schematically illustrated control and driver circuit 120.
- Submount 115, 116 and monitor diode 111, 112 are positioned at a right angle to one another, so that on the one hand the monitor diode with its optically active surface projects beyond the spacer and on the other hand there is space on the spacer for contact pads for connecting the bonding wires 119.
- the two monitor diodes 111, 112 are usually used in such a way that the optical output power of the laser diodes 102 is regulated with the aid of a monitor diode 111, while the other laser diode 112 brings about a safety shutdown in the event that the laser power exceeds a predetermined limit value.
- Such regulations are known per se.
- the flip-chip assembly adjusts the two isolated components by turning one chip and then positioning it on the other chip in a workpiece carrier.
- the disadvantage of this method is that one component must be positioned in a workpiece carrier after being separated. The process is time consuming and the small size of the individual chips (about 2mm x 2mm) difficult to handle. The process is also cost-intensive, since it is a single chip process, ie complex and expensive one-off productions.
- the present invention is therefore based on the object of a photodiode arrangement and a method for. To provide a connection between a first semiconductor component and a second semiconductor component, which enable a connection of the semiconductor components using standard processes and thereby in a cost-effective and effective manner.
- the solution according to the invention is characterized by a photodiode arrangement in which a photodiode and a submount for contacting the photodiode are connected to one another by eutectic bonding. Both elements have a corresponding metallization on the side facing each other.
- a submount is understood to mean a carrier element for the photodiode.
- the invention provides a method for producing a connection between a first semiconductor component and a second semiconductor component, which have a different outer contour. In particular, the method serves to connect a photodiode to a submount for producing a photodiode arrangement.
- the method has the following steps: a) producing a multiplicity of first semiconductor components on a first wafer, b) producing a multiplicity of second semiconductor components on a 'second wafer, c) applying a metallization to the first semiconductor components of the first wafer, d) applying a metallization on the second semiconductor components of the second wafer, e) formation of trenches in the first and / or the second semiconductor components, then f) connection of the two wafers by eutectic bonding of the respective metallizations, the resulting wafer composite having a front and a back , then g) separating the front of the array of wafers according to a first outer contour of the first semiconductor components to be separated, only the first wafer being cut, and subsequently h) separating the back of the composite wafer according to a second outer contour of the second semiconductor to be separated construction elements, with only the second wafer being cut.
- the semiconductor components to be connected are thus already connected to one another in the wafer assembly. This is done by eutectic bonding of the metallizations formed on the respective semiconductor components. For example, there is gold metallization on one wafer and one on the other wafer Gold-tin plating.
- the trenches that are etched into the respective surface before the bonding process ensure that the photodiode and the submount only connect to one another at defined points. So the formation of trenches makes it topographical
- the front side is separated first and then - preferably after the wafer assembly is turned - the back side.
- the separation is preferably carried out by sawing the respective side. It is not the complete wafer composite that is separated, but only the one above
- end components can be produced in the wafer process which have different contours, in particular are arranged at an angle to one another.
- the method according to the invention is extremely effective and time-saving, since up to several thousand semiconductor components can be mounted on one another at the same time. Proven procedures are advantageously combined in a new way and existing logistics chains can be used.
- the method can be applied to all semiconductor components which are individually connected to one another with flip-chip assembly. It only has to be possible to apply the metallizations required for eutectic bonding to the respective semiconductor components already in the wafer assembly. By using eutectic substance mixtures (e.g. gold-tin with gold), the melting point for the bonding of the metallizations is reduced, so that structures of the semiconductor components formed on the wafers, for example optically active areas of a photodiode, are not destroyed or damaged when the wafers are bonded.
- eutectic substance mixtures e.g. gold-tin with gold
- the respective semiconductor components i.e. in particular one photodiode and one submount in each case, are preferably silicon chips. Silicon is a relatively inexpensive material and can rely on tried and tested processing methods.
- Figure 1 is a side view of a
- Photodiode arrangement with a photodiode and a submount for carrying and contacting the
- FIG. 2 shows two wafers to be connected by means of eutectic bonding before the connection
- FIG. 3 shows the two wafers connected by eutectic bonding
- FIG. 4 shows a first singulation process on one side of the interconnected wafers
- FIG. 5 shows a second singulation process on the other side of the interconnected wafers
- FIG. 7 shows a photodiode arrangement known from the prior art.
- FIG. 1 shows a photodiode arrangement in which a monitor diode 1 is arranged on a spacer 2. Both the spacer 2 and an array 3 of vertically emitting semiconductor lasers (VCSEL) are positioned on a common carrier 4 in such a way that a lateral one
- VCSEL vertically emitting semiconductor lasers
- the monitor diode 1 is preferably a silicon photodiode.
- the submount 2 is preferably a silicon chip.
- the two components 1, 2 each have metallizations.
- the metallizations of the spacer 2 can each be connected to a bonding wire via a contact pad 21.
- the two components 1, 2 are connected via eutectic bonding even in the wafer assembly, as a result of which the monitor diode 1 and the submount 2 are electrically and mechanically connected to one another in a region 6. This is explained in more detail below with reference to FIGS. 2 to 5.
- a multiplicity of semiconductor components 1 ′, 2 ′ are respectively structured on the front side of a first wafer 7 and the front side of a second wafer 8.
- the semiconductor components 1 'of the first wafer 7 are photodiodes with optically active areas and the semiconductor components 2' of the second wafer 8 are submounts, as are used in the arrangement in FIG. 1.
- the surfaces of the two wafers 7, 8 are placed on top of one another and directly connected to one another by means of eutectic bonding.
- the two wafers 7, 8 each have a metallization 12 ', 21'.
- the one metallization is preferably a gold metallization 12 '
- the other metallization is preferably a gold-tin metallization 21'.
- trenches or recesses 9 are provided in the surface of at least one wafer. The recesses 9 ensure that a connection between the two wafers takes place only in defined areas. Adjustment aids (so-called fiducials) are also attached to the wafers 7, 8 (not shown). The eutectic bonding of the two wafers is carried out in a manner known per se.
- the wafer 7 is separated by sawing along the lines 10-b. This is the one to be separated
- Semiconductor components give a second desired outer contour, that of the outer contour of the first
- Semiconductor components 2 deviates. After the second wafer 7 has also been separated, the end components already connected are units from the two semiconductor components 1, 2, which are, for example, a monitor diode 1 and a submount 2 according to FIG. 1.
- the wafers 7, 8 can also be separated by other separation techniques.
- FIG. 6 shows the metallizations of the two semiconductor components for the example of a monitor diode 1 and a submount 2.
- the monitor diode 1 has an optically active region 14 which is electrically contacted via metallizations 12, 13.
- the metallizations 12, 13 each merge into flat metallization regions 12a, 13a.
- the submount 2 has two contact pads 21 for contacting the monitor diode 1, which are each connected to metallizations 22, 23.
- the metallizations 22, 23 correspond to the metallizations 12, 13 of the monitor diode in a crossover area in which the monitor diode 1 and the submount 2 are eutectically bonded to one another and form planar metallization regions 22a, 23a, so that the respective metallizations 22a, 12a; 23a, 13a lie one on top of the other.
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Light Receiving Elements (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
Beschreibungdescription
Bezeichnung der Erfindung: Photodiodenanordnung und Verfahren zur Herstellung einer Verbindung zwischen einem ersten Halbleiterbauelement und einem zweiten Halbleiterbauelement.DESCRIPTION OF THE INVENTION: Photodiode arrangement and method for producing a connection between a first semiconductor component and a second semiconductor component.
Die Erfindung betrifft eine Photodiodenanordnung mit einer Photodiode und einem Submount, über den eine elektrische Kontaktierung der Photodiode erfolgt, und ein Verfahren zur Herstellung einer Verbindung zwischen einem erstenThe invention relates to a photodiode arrangement with a photodiode and a submount, via which electrical contact is made with the photodiode, and a method for establishing a connection between a first
Halbleiterbauelement und einem zweiten Halbleiterbauelement, insbesondere zwischen einer Photodiode und einem Submount für eine Photodiode, wobei die miteinander verbundenen Halbleiterbauelemente eine unterschiedliche Außenkontur aufweisen.Semiconductor component and a second semiconductor component, in particular between a photodiode and a submount for a photodiode, the interconnected semiconductor components having a different outer contour.
Aus der DE 197 09 842 Cl ist eine elektrooptische Koppelbaugruppe mit einer Laserdiodenanordnung bekannt, bei der eine Mehrzahl von vertikal emittierenden VCSEL- Laserdioden in einem Array angeordnet sind. Den Laserdioden sind in einer Ebene angeordnete Lichtwellenleiter zugeordnet, deren kopplungsseitige Stirnflächen eine Strahlumlenkung des von den Laserdioden ausgestrahlten Lichts in die Lichtwellenleiter bewirken.From DE 197 09 842 C1 an electro-optical coupling module with a laser diode arrangement is known, in which a plurality of vertically emitting VCSEL laser diodes are arranged in an array. The laser diodes are assigned optical fibers arranged in one plane, the end faces of which on the coupling side cause the light emitted by the laser diodes to be deflected into the optical fibers.
Es ist bekannt, bei derartigen Laserdiodenanordnungen eine oder mehrere Monitordioden vorzusehen, über die eine Überwachung und Steuerung der Laserdiodenanordnung erfolgt.In such laser diode arrangements, it is known to provide one or more monitor diodes via which the laser diode arrangement is monitored and controlled.
Einen entsprechenden, im Stand der Technik bekannten Aufbau zeigt schematisch die Figur 7. Danach ist auf einem Submount 100 ein Laserdiodenarray 101 angeordnet, das im dargestellten Ausführungsbeispiel aus sechzehn VCSEL-Dioden 102 besteht. Zwölf dieser Laserdioden 102 dienen der Datenkommunikationen und ihnen ist dementsprechend jeweils ein schematisch dargestellter Lichtwellenleiter 103 zugeordnet. Den beiden am Rand des Arrays 101 befindlichen Laserdioden 104, 105 ist jeweils eine aus Gallium-Arsenid bestehende Monitordiode 111, 112 zugeordnet, deren optisch aktive Fläche direkt oberhalb der jeweils äußersten Laserdiode 104, 105 positioniert und diesen zugewandt ist.A corresponding structure known in the prior art is shown schematically in FIG. 7. Thereafter, a laser diode array 101 is arranged on a submount 100, which in the exemplary embodiment shown consists of sixteen VCSEL diodes 102. Twelve of these laser diodes 102 are used for data communications and accordingly a schematically represented optical waveguide 103 is assigned to each of them. The two laser diodes 104, 105 located at the edge of the array 101 A monitor diode 111, 112 consisting of gallium arsenide is assigned, the optically active surface of which is positioned directly above the outermost laser diode 104, 105 and faces it.
Alternativ .wäre es auch möglich, die optisch aktive Fläche der Photodiode an der den Laserdioden 104, 105 abgewandten Seite, also oben anzubringen. Es wäre dann aber eine Umlenkoptik erforderlich, um den Laserstrahl auf die optisch aktive Fläche der Monitordiode zu lenken.Alternatively, it would also be possible to mount the optically active surface of the photodiode on the side facing away from the laser diodes 104, 105, that is to say at the top. A deflection optics would then be required in order to direct the laser beam onto the optically active surface of the monitor diode.
Die Monitordiode 111, 112 ist jeweils in einem Träger 113, 114 ausgebildet, der an einem als Abstandselement bzw. Spacer dienenden Submount 115, 116 befestigt ist. Bei dem Submount handelt es sich um einen Keramikträger.The monitor diode 111, 112 is formed in each case in a carrier 113, 114 which is attached to a submount 115, 116 serving as a spacer. The submount is a ceramic carrier.
Die Kontaktierung der Monitordioden 111-, 112 und auch der Laserdioden 102, 104, 105 erfolgt über Bond-Drähte 117, die über Metallisierungen 118 und weitere Bonddrähte 119 mit Kontakten eines schematisch dargestellten Steuer- und Treiberschaltkreises 120 verbunden sind.The contacting of the monitor diodes 111-, 112 and also of the laser diodes 102, 104, 105 takes place via bond wires 117, which are connected via metallizations 118 and further bond wires 119 to contacts of a schematically illustrated control and driver circuit 120.
Submount 115, 116 und Monitordiode 111, 112 sind in einem rechten Winkel zueinander positioniert, so dass zum einen die Monitordiode mit ihrer optisch aktiven Fläche über den Spacer hinausragt und zum anderen auf dem Spacer Platz für Kontaktpads zum Anschluß der Bonddrähte 119 ist.Submount 115, 116 and monitor diode 111, 112 are positioned at a right angle to one another, so that on the one hand the monitor diode with its optically active surface projects beyond the spacer and on the other hand there is space on the spacer for contact pads for connecting the bonding wires 119.
Die beiden Monitordioden 111, 112 werden üblicherweise derart eingesetzt, daß mit Hilfe einer Monitordiode 111 die optische Ausgangsleistung der Laserdioden 102 geregelt wird, während die andere Laserdiode 112 eine Sicherheitsabschaltung für den Fall bewirkt, daß die Laserleistung über einen vorgegebenen Grenzwert hinausgeht. Derartige Regelungen sind an sich bekannt. Zur elektrischen und mechanischen Verbindung von Submount 115, 116 und Monitordiode 111, 112 ist es bekannt, die beiden Chips durch Flip-Chip Montage zu verbinden. Die Flip-Chip Montage justiert die beiden vereinzelten Bauteile durch Wenden des einen Chips und anschließendem Positionieren auf dem anderen, in einem Werkstückträger liegenden Chip. Nachteilig muss bei diesem Verfahren das eine Bauteil nach dem Vereinzeln in einem Werkstückträger positioniert werden. Das Verfahren ist zeitaufwendig und die geringe Größe der vereinzelten Chips (etwa 2mm x 2mm) schwer zu handhaben. Auch ist das Verfahren kostenintensiv, das es sich um einen Einzelchipprozess, d.h. um aufwendige und teure Einzelanfertigungen handelt.The two monitor diodes 111, 112 are usually used in such a way that the optical output power of the laser diodes 102 is regulated with the aid of a monitor diode 111, while the other laser diode 112 brings about a safety shutdown in the event that the laser power exceeds a predetermined limit value. Such regulations are known per se. For the electrical and mechanical connection of submount 115, 116 and monitor diode 111, 112, it is known to connect the two chips by flip-chip assembly. The flip-chip assembly adjusts the two isolated components by turning one chip and then positioning it on the other chip in a workpiece carrier. The disadvantage of this method is that one component must be positioned in a workpiece carrier after being separated. The process is time consuming and the small size of the individual chips (about 2mm x 2mm) difficult to handle. The process is also cost-intensive, since it is a single chip process, ie complex and expensive one-off productions.
Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, eine Photodiodenanordnung und ein Verfahren zur . Herstellung einer Verbindung zwischen einem ersten Halbleiterbauelement und einem zweiten Halbleiterbauelement zur Verfügung zu stellen, die eine Verbindung der Halbleiterbauelemente unter Verwendung von Standardprozessen und dabei in kostengünstiger und effektiver Weise ermöglichen.The present invention is therefore based on the object of a photodiode arrangement and a method for. To provide a connection between a first semiconductor component and a second semiconductor component, which enable a connection of the semiconductor components using standard processes and thereby in a cost-effective and effective manner.
Diese Aufgabe wird erfindungsgemäß durch eine Photodiodenanordnung mit den Merkmalen des Anspruchs 1 und ein Verfahren mit den Merkmalen des Anspruchs 8 gelöst.This object is achieved according to the invention by a photodiode arrangement with the features of claim 1 and a method with the features of claim 8.
Bevorzugte und vorteilhafte Ausgestaltungen der Erfindung sind in den Unteransprüchen angegeben.Preferred and advantageous embodiments of the invention are specified in the subclaims.
Danach zeichnet sich die erfindungsgemäße Lösung in einem ersten Aspekt durch eine Photodiodenanordnung aus, bei der eine Photodiode und ein Submount zur Kontaktierung der Photodiode durch eutektisches Bonden miteinander verbunden sind. Dabei weisen beide Elemente auf der einander zugewandten Seite jeweils eine entsprechende Metallisierung auf. Unter einem Submount wird ein Trägerelement für die Photodiode verstanden. In einem zweiten Aspekt stellt die Erfindung ein Verfahren zur Herstellung einer Verbindung zwischen einem ersten Halbleiterbauelement und einem zweiten Halbleiterbauelement zur Verfügung, die eine unterschiedliche Außenkontur aufweisen. Insbesondere dient das Verfahren der Verbindung einer Photodiode mit einem Submount zur Herstellung einer Photodiodenanordnung gemäß Anspruch 1.According to a first aspect, the solution according to the invention is characterized by a photodiode arrangement in which a photodiode and a submount for contacting the photodiode are connected to one another by eutectic bonding. Both elements have a corresponding metallization on the side facing each other. A submount is understood to mean a carrier element for the photodiode. In a second aspect, the invention provides a method for producing a connection between a first semiconductor component and a second semiconductor component, which have a different outer contour. In particular, the method serves to connect a photodiode to a submount for producing a photodiode arrangement.
Das Verfahren weist die folgenden Schritte auf: a) Herstellen einer Vielzahl erster Halbleiterbauelemente auf einem ersten Wafer, b) Herstellen einer Vielzahl zweiter Halbleiterbauelemente auf einem' zweiten Wafer, dabei c) Anbringen einer Metallisierung auf den ersten Halbleiterbauelementen des ersten Wafers, d) Anbringen einer Metallisierung auf den zweiten Halbleiterbauelementen des zweiten Wafers, e) Ausbildung von Gräben in den ersten und/oder den zweiten Halbleiterbauelemenen, danach f) Verbinden der beiden Wafer durch eutektisches Bonden der jeweiligen Metallisierungen, wobei der entstandene Waferverbund eine Vorder- und eine Rückseite aufweist, danach g) Vereinzelnen der Vorderseite des Wäferverbunds entsprechend einer ersten Außenkontur der zu vereinzelnden ersten Halbleiterbauelemente, wobei nur der erste Wafer durchtrennt wird, und anschließend h) Vereinzelnen der Rückseite des Wäferverbunds entsprechend einer zweiten Außenkontur der zu vereinzelnden zweiten Halbleiterbauelemente, wobei nur der zweite Wafer durchtrennt wird.The method has the following steps: a) producing a multiplicity of first semiconductor components on a first wafer, b) producing a multiplicity of second semiconductor components on a 'second wafer, c) applying a metallization to the first semiconductor components of the first wafer, d) applying a metallization on the second semiconductor components of the second wafer, e) formation of trenches in the first and / or the second semiconductor components, then f) connection of the two wafers by eutectic bonding of the respective metallizations, the resulting wafer composite having a front and a back , then g) separating the front of the array of wafers according to a first outer contour of the first semiconductor components to be separated, only the first wafer being cut, and subsequently h) separating the back of the composite wafer according to a second outer contour of the second semiconductor to be separated construction elements, with only the second wafer being cut.
Erfindungsgemäß werden die zu verbindenden Halbleiterbauelemente somit bereits im Waferverbund miteinander verbunden. Dies erfolgt durch eutektisches Bonden der auf den jeweiligen Halbleiterbauelementen ausgebildeten Metallisierungen. Beispielsweise befindet sich auf dem einen Wafer eine Gold-Metallisierung und auf dem anderen Wafer eine Gold-Zinn-Metallisierung. Durch die Gräben, die vor dem Bondvorgang in die jeweilige Oberfläche geätzt werden, wird sichergestellt, dass sich die Photodiode und der Submount nur an definierten Stellen miteinander verbinden. Es wird also durch die Ausbildung von Gräben eine topographischeAccording to the invention, the semiconductor components to be connected are thus already connected to one another in the wafer assembly. This is done by eutectic bonding of the metallizations formed on the respective semiconductor components. For example, there is gold metallization on one wafer and one on the other wafer Gold-tin plating. The trenches that are etched into the respective surface before the bonding process ensure that the photodiode and the submount only connect to one another at defined points. So the formation of trenches makes it topographical
Bearbeitung der Wafer an den Stellen bereitgestellt, an denen keine Verbindung der Wafer benötigt wird.Processing of the wafers provided at the points where no connection of the wafers is required.
Zur Herstellung unterschiedlicher Außenkonturen der zu vereinzelnden Halbleiterbauelemente auf den beiden Seiten des Waferverbundes wird zunächst die Vorderseite und dann - bevorzugt nach einem Wenden den Waferverbundes - die Rückseite vereinzelt. Das Vereinzeln erfolgt bevorzugt durch Sägen der jeweiligen Seite. Es wird also nicht der komplette Waferverbund getrennt, sondern nur die jeweils oben zumTo produce different outer contours of the semiconductor components to be separated on the two sides of the wafer assembly, the front side is separated first and then - preferably after the wafer assembly is turned - the back side. The separation is preferably carried out by sawing the respective side. It is not the complete wafer composite that is separated, but only the one above
Liegen kommende..Komponente. Es können dadurch Endkomponenten im Waferprozess hergestellt werden, die unterschiedliche Konturen aufweisen, insbesondere winklig zueinander angeordnet sind.Coming components. As a result, end components can be produced in the wafer process which have different contours, in particular are arranged at an angle to one another.
Nach Vereinzelung werden die Endkomponenten aus dem Waferverbund gelöst und zur weiteren Verarbeitung einer automatisierten Vorrichtung zugeführt, bei der sich beispielsweise um ein sogenanntes „Blue-Tapeu, einen Werkstückträger handelt.After isolation the final components are dissolved from the wafer composite, and fed for further processing of an automated device, this is for example a so-called "blue tape u, a workpiece carrier in the.
Das erfindungsgemäße Verfahren ist äußerst effektiv und zeitsparend, da bis zu mehrere tausend Halbleiterbauelemente gleichzeitig aufeinander montiert werden können. Dabei werden mit Vorteil erprobte Verfahren auf neue Weise miteinander kombiniert und kann auf vorhandene Logistigketten zurückgegriffen werden. Das Verfahren ist auf alle Halbleiterbauelemente anwendbar, die mit Flip-Chip Montage jeweils einzeln miteinander verbunden werden. Dabei muss es lediglich möglich sein, bereits im Waferverband die für ein eutektisches Bonden erforderlichen Metallisierungen auf die jeweiligen Halbleiterbauelemente aufzubringen. Durch Verwendung eutektischer Stoffgemische (z.B. Gold-Zinn mit Gold) wird der Schmelzpunkt für das Bonden der Metallisierungen herabgesetzt, so dass auf den Wafern ausgebildete Strukturen der Halbleiterbauelementen, beispielsweise optisch aktive Bereiche einer Photodiode, beim Bonden der Wafer nicht zerstört bzw. beschädigt werden.The method according to the invention is extremely effective and time-saving, since up to several thousand semiconductor components can be mounted on one another at the same time. Proven procedures are advantageously combined in a new way and existing logistics chains can be used. The method can be applied to all semiconductor components which are individually connected to one another with flip-chip assembly. It only has to be possible to apply the metallizations required for eutectic bonding to the respective semiconductor components already in the wafer assembly. By using eutectic substance mixtures (e.g. gold-tin with gold), the melting point for the bonding of the metallizations is reduced, so that structures of the semiconductor components formed on the wafers, for example optically active areas of a photodiode, are not destroyed or damaged when the wafers are bonded.
Bevorzugt befinden sich auf den Wafern Justagemarken, die eine genaue Positionierung der jeweiligen Wafer aufeinander sicherstellen.There are preferably alignment marks on the wafers which ensure precise positioning of the respective wafers on one another.
Bei den jeweiligen Halbleiterbauelementen, d.h. insbesondere jeweils einer Photodiode und einem Submount, handelt sich bevorzugt um Siliziumchips. Es handelt sich bei Silizium um ein relativ kostengünstiges Material und kann auf bereits erprobte Bearbeitungsverfahren zurückgegriffen werden.With the respective semiconductor components, i.e. in particular one photodiode and one submount in each case, are preferably silicon chips. Silicon is a relatively inexpensive material and can rely on tried and tested processing methods.
Die Erfindung wird nochfolgend unter Bezugnahme auf die Figuren der Zeichnung anhand mehrerer Ausführungsformen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the figures of the drawing using several embodiments. Show it:
Figur 1 eine seitliche Ansicht einerFigure 1 is a side view of a
Photodiodenanordnung mit einer Photodiode und einem Submount zum Tragen und Kontaktieren derPhotodiode arrangement with a photodiode and a submount for carrying and contacting the
Photodiode;Photodiode;
Figur 2 zwei mittels eutektischen Bondens zu verbindenende Wafer vor dem Verbinden;FIG. 2 shows two wafers to be connected by means of eutectic bonding before the connection;
Figur 3 die beiden durch eutektisches Bonden verbundenen Wafer;FIG. 3 shows the two wafers connected by eutectic bonding;
Figur 4 einen ersten Vereinzelungsprozess an der einen Seite der miteinander verbundenen Wafer; Figur 5 einen zweiten Vereinzelungsprozess an der anderen Seite der miteinander verbundenen Wafer;FIG. 4 shows a first singulation process on one side of the interconnected wafers; FIG. 5 shows a second singulation process on the other side of the interconnected wafers;
Figur 6 in Draufsicht eine aus demFigure 6 in plan view one from the
Vereinzelungsprozess hervorgeganege Photodiodenanordnung undIsolation process emerged photodiode arrangement and
Figur 7 eine aus dem Stand der Technik bekannte Photodiodenanordnung.FIG. 7 shows a photodiode arrangement known from the prior art.
Zur Erläuterung des Hintergrundes des Erfindung war eingangs eine im Stand der Technik bekannte Photodiodenanordnung anhand der Figur 7 beschrieben worden.To explain the background of the invention, a photodiode arrangement known in the prior art was initially described with reference to FIG. 7.
Die Figur 1 zeigt eine Photodiodenanordnung, bei der eine Monitordiode 1 auf einem Spacer 2 angeordnet ist. Sowohl der Spacer 2 als auch ein Array 3 vertikal emmittierender Halbleiterlaser (VCSEL) sind derart auf einem gemeinsamen Träger 4 positioniert, dass von einem seitlichenFIG. 1 shows a photodiode arrangement in which a monitor diode 1 is arranged on a spacer 2. Both the spacer 2 and an array 3 of vertically emitting semiconductor lasers (VCSEL) are positioned on a common carrier 4 in such a way that a lateral one
Halbleiterlaser des Arrays ausgestrahltes Licht von der Monitordiode 1 direkt detektiert wird, die mit ihrer nach unten ausgerichteten optisch aktiven Schicht 14 über den Spacer 2 ragt.Semiconductor laser of the array emitted light is directly detected by the monitor diode 1, which projects with its downwardly oriented optically active layer 14 over the spacer 2.
Bei der Monitordiode 1 handelt es sich bevorzugt um eine Silizium-Photodiode. Ebenso ist der Submount 2 bevorzugt ein Silizium-Chip. Die beiden Komponenten 1, 2 weisen jeweils Metallisierungen auf. Die Metallisierungen des Spacers 2 sind dabei jeweils über einen Kontaktpad 21 mit einem Bonddraht verbindbar. Die Verbindung der beiden Komponenten 1, 2 erfolgt über ein eutektisches Bonden noch im Waferverbund, wodurch die Monitordiode 1 und der Submount 2 in einem Bereich 6 elektrisch und auch mechanisch miteinander verbunden werden. Dies wird nachfolgend anhand der Figuren 2 bis 5 näher erläutert. Gemäß Figur 2 werden auf der Vorderseite eines ersten Wafers 7 und der Vorderseite eines zweiten Wafer 8 in an sich bekannter Weise jeweils eine Vielzahl von Halbleiterbauelementen 1', 2' strukturiert. Insbesondere handelt es sich bei den Halbleiterbauelementen 1' des ersten Wafers 7 um Photodioden mit optisch aktiven Flächen und bei den Halbleiterbauelementen 2' des zweiten Wafers 8 um Submounts, wie sie bei der Anordnung der Fig. 1 verwendet werden.The monitor diode 1 is preferably a silicon photodiode. Likewise, the submount 2 is preferably a silicon chip. The two components 1, 2 each have metallizations. The metallizations of the spacer 2 can each be connected to a bonding wire via a contact pad 21. The two components 1, 2 are connected via eutectic bonding even in the wafer assembly, as a result of which the monitor diode 1 and the submount 2 are electrically and mechanically connected to one another in a region 6. This is explained in more detail below with reference to FIGS. 2 to 5. According to FIG. 2, a multiplicity of semiconductor components 1 ′, 2 ′ are respectively structured on the front side of a first wafer 7 and the front side of a second wafer 8. In particular, the semiconductor components 1 'of the first wafer 7 are photodiodes with optically active areas and the semiconductor components 2' of the second wafer 8 are submounts, as are used in the arrangement in FIG. 1.
Die beiden Wafer 7, 8 werden mit Ihren Oberflächen aufeinandergelegt und unmittelbar mittels eutektischen Bondens miteinander verbunden. Gemäß Figur 3 wei-sen die beiden Wafer 7, 8 dabei jeweils eine Metallisierung 12', 21' auf. Bei der einen Metallisierung handelt es sich bevorzugt um eine Gold-Metallisierung 12', bei der anderen Metallisierung bevorzugt um eine Gold-Zinn-Metallisierung 21' . Des weiteren sind in der Oberfläche mindestens eines Wafers Gräben bzw. Aussparungen 9 vorgesehen. Die Aussparungen 9 sorgen dafür, das eine Verbindung zwischen den beiden Wafern nur in definierten Bereichen erfolgt. Auch sind auf den Wafern 7, 8 Justagehilfen (sogenannte Fiducials) angebracht (nicht dargestellt) . Das eutektische Bonden der beiden Wafer erfolgt in an sich bekannter Weise.The surfaces of the two wafers 7, 8 are placed on top of one another and directly connected to one another by means of eutectic bonding. According to FIG. 3, the two wafers 7, 8 each have a metallization 12 ', 21'. The one metallization is preferably a gold metallization 12 ', the other metallization is preferably a gold-tin metallization 21'. Furthermore, trenches or recesses 9 are provided in the surface of at least one wafer. The recesses 9 ensure that a connection between the two wafers takes place only in defined areas. Adjustment aids (so-called fiducials) are also attached to the wafers 7, 8 (not shown). The eutectic bonding of the two wafers is carried out in a manner known per se.
Nach dem Verbinden der beiden Wafer 7, 8 ist es erforderlich, eine Vereinzelung der gewünschten Komponenten vorzunehmen. Dabei wird gemäß Figur 4 zunächst lediglich der eine Wafer 8 des Wäferverbunds 7, 8 vereinzelt. Dies erfolgt durch Sägen der einen Seite des Waferverbundes 7, 8 entlang den Linien 10-a. Der eine Wafer 8 wird dabei entlang Linien 10-a vereinzelt, die den zu vereinzelnden Halbleiterbauelementen 1' eine erste gewünschte Außenkontur geben. Die im Bereich der Aussparungen 9 befindlichen Restbereiche 81, die nun keine Verbindung mit der Waferverbund 7, 8 mehr haben, werden entfernt, wobei die mit dem anderen Wafer 7 eutektisch gebondeten Bereiche 82 übrig bleiben, die die gewünschten Halbleiterbauelemente 2 darstellen.After the two wafers 7, 8 have been connected, it is necessary to separate the desired components. According to FIG. 4, only the one wafer 8 of the wafer composite 7, 8 is initially separated. This is done by sawing one side of the wafer composite 7, 8 along the lines 10-a. The one wafer 8 is separated along lines 10-a, which give the semiconductor components 1 'to be separated a first desired outer contour. The remaining areas 81 located in the area of the recesses 9, which are now no longer connected to the wafer assembly 7, 8, are removed, the one with the other wafer 7 being eutectic bonded regions 82 remain, which represent the desired semiconductor components 2.
Nach Vereinzeln des einen Wafers 8 des Waferverbundes 7, 8 wird die andere Seite bzw. der andere Wafer 7 desAfter separating the one wafer 8 of the wafer assembly 7, 8, the other side or the other wafer 7 of the
Waferverbundes 7, 9 vereinzelt, wozu dieser bevorzugt, aber nicht notwendigerweise gewendet wird (damit nur an einer Seite ein Sägewerkzeug angeordnet werden muss) . Gemäß Figur 5 wird der Wafer 7 durch Sägen entlang den Linien 10-b vereinzelt. Dabei wird den zu vereinzelndenWafer composite 7, 9 isolated, for which purpose this is preferred, but not necessarily turned (so that a sawing tool only has to be arranged on one side). According to FIG. 5, the wafer 7 is separated by sawing along the lines 10-b. This is the one to be separated
Halbleiterbauelementen eine zweite gewünschte Außenkontur geben, die von der Außenkontur der erstenSemiconductor components give a second desired outer contour, that of the outer contour of the first
Halbleiterbauelemente 2 abweicht. Nach Vereinzeln auch des zweiten Wafers 7 verbleiben als Endkomponenten bereits verbundene Einheiten aus den beiden Halbleiterbauelementen 1, 2, bei den es sich beispielsweise um eine Monitordiode 1 und einen Submount 2 entsprechend Fig. 1 handelt.Semiconductor components 2 deviates. After the second wafer 7 has also been separated, the end components already connected are units from the two semiconductor components 1, 2, which are, for example, a monitor diode 1 and a submount 2 according to FIG. 1.
Statt eines Vereinzeins durch Sägen können die Wafer 7, 8 auch durch andere Trenntechniken vereinzelt werden.Instead of being separated by sawing, the wafers 7, 8 can also be separated by other separation techniques.
Figur 6 zeigt die Metallisierungen der beiden Halbleiterbauelemente für das Beispiel einer Monitordiode 1 und eines Submounts 2. Die Monitordiode 1 weist einen optisch aktiven Bereich 14 auf, die über Metallisierungen 12, 13 elektrisch Kontaktiert wird. Die Metallisierungen 12, 13 gehen jeweils in flächige Metallisierungsbereiche 12a, 13a über. Der Submount 2 weist zwei Kontaktpads 21 zur Kontaktierung der Monitordiode 1 auf, die jeweils mit Metallisierungen 22, 23 verbunden sind. Die Metallisierungen 22, 23 entsprechen in ihrer Geometrie in einem Überscheidungsbereich, in dem die Monitordiode 1 und der Submount 2 eutektisch miteinander gebondet sind, den Metallisierungen 12, 13 der Monitordiode und bilden flächige Metallisierungsbereiche 22a, 23a aus, so dass die jeweiligen Metallisierungen 22a, 12a; 23a, 13a aufeinanderliegen. FIG. 6 shows the metallizations of the two semiconductor components for the example of a monitor diode 1 and a submount 2. The monitor diode 1 has an optically active region 14 which is electrically contacted via metallizations 12, 13. The metallizations 12, 13 each merge into flat metallization regions 12a, 13a. The submount 2 has two contact pads 21 for contacting the monitor diode 1, which are each connected to metallizations 22, 23. In terms of their geometry, the metallizations 22, 23 correspond to the metallizations 12, 13 of the monitor diode in a crossover area in which the monitor diode 1 and the submount 2 are eutectically bonded to one another and form planar metallization regions 22a, 23a, so that the respective metallizations 22a, 12a; 23a, 13a lie one on top of the other.
Claims
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/DE2002/000067 WO2003058720A1 (en) | 2002-01-09 | 2002-01-09 | Photodiode array and method for establishing a link between a first semiconductor element and a second semiconductor element |
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| EP1464084A1 true EP1464084A1 (en) | 2004-10-06 |
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| EP02704576A Withdrawn EP1464084A1 (en) | 2002-01-09 | 2002-01-09 | Photodiode array and method for establishing a link between a first semiconductor element and a second semiconductor element |
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| US (1) | US7476906B2 (en) |
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| WO (1) | WO2003058720A1 (en) |
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| DE102006017293A1 (en) | 2005-12-30 | 2007-07-05 | Osram Opto Semiconductors Gmbh | Method for production of optically pumpable semiconductor device, involves providing connection carrier assembly comprising plurality of connection carriers, which are mechanically and fixedly connected to one another |
| WO2011056733A2 (en) | 2009-11-03 | 2011-05-12 | Rbd Solutions Llc | Fiber optic devices and methods of manufacturing fiber optic devices |
| DE102012107409B4 (en) * | 2012-08-13 | 2022-06-15 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Method of manufacturing a semiconductor laser element |
| CN103928364B (en) * | 2014-04-14 | 2016-09-28 | 江苏艾特曼电子科技有限公司 | A kind of for detecting the structure of alloying level in eutectic bonding |
| CN109632791B (en) * | 2018-11-12 | 2022-03-25 | 航天科工防御技术研究试验中心 | Method for evaluating bonding quality of semiconductor device bonding wire |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4143385A (en) | 1976-09-30 | 1979-03-06 | Hitachi, Ltd. | Photocoupler |
| JPS59220982A (en) * | 1983-05-31 | 1984-12-12 | Sumitomo Electric Ind Ltd | Package for photo element |
| JPH0746747B2 (en) * | 1986-09-09 | 1995-05-17 | 松下電器産業株式会社 | Semiconductor laser bonding method |
| DE59305898D1 (en) * | 1993-12-22 | 1997-04-24 | Siemens Ag | Optoelectronic component and method for its production |
| US5535296A (en) * | 1994-09-28 | 1996-07-09 | Optobahn Corporation | Integrated optoelectronic coupling and connector |
| JP3613838B2 (en) | 1995-05-18 | 2005-01-26 | 株式会社デンソー | Manufacturing method of semiconductor device |
| DE19709842C1 (en) | 1997-02-28 | 1998-10-15 | Siemens Ag | Electro-optical coupling assembly |
| US20020028390A1 (en) * | 1997-09-22 | 2002-03-07 | Mohammad A. Mazed | Techniques for fabricating and packaging multi-wavelength semiconductor laser array devices (chips) and their applications in system architectures |
| DE19838518A1 (en) * | 1998-08-25 | 2000-03-02 | Bosch Gmbh Robert | arrangement |
| JP3486378B2 (en) | 1998-09-14 | 2004-01-13 | シーメンス アクチエンゲゼルシヤフト | Method for manufacturing a photoelectric device |
| US7295783B2 (en) * | 2001-10-09 | 2007-11-13 | Infinera Corporation | Digital optical network architecture |
-
2002
- 2002-01-09 WO PCT/DE2002/000067 patent/WO2003058720A1/en active Application Filing
- 2002-01-09 US US10/501,209 patent/US7476906B2/en not_active Expired - Lifetime
- 2002-01-09 EP EP02704576A patent/EP1464084A1/en not_active Withdrawn
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| US7476906B2 (en) | 2009-01-13 |
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