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EP0621982A1 - Lead frame and semiconductor device using same - Google Patents

Lead frame and semiconductor device using same

Info

Publication number
EP0621982A1
EP0621982A1 EP93924830A EP93924830A EP0621982A1 EP 0621982 A1 EP0621982 A1 EP 0621982A1 EP 93924830 A EP93924830 A EP 93924830A EP 93924830 A EP93924830 A EP 93924830A EP 0621982 A1 EP0621982 A1 EP 0621982A1
Authority
EP
European Patent Office
Prior art keywords
leads
outer leads
lead frame
lead
base film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP93924830A
Other languages
German (de)
French (fr)
Japanese (ja)
Inventor
Fumio Shinko Electric Ind. Co. Ltd. Kuraishi
Kazuhito Shinko Electric Ind. Co. Ltd. Yumoto
Mamoru Shinko Electric Ind. Co. Ltd. Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of EP0621982A1 publication Critical patent/EP0621982A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a lead frame and a semiconductor device using the same lead frame .
  • This invention also relates to a process for making such a lead frame.
  • a TAB tape can be made by forming a thin conductive film on an electrically insulative base film and etching the conductive film to form a desired conductive pattern .
  • the thickness of such conductive patterns can be reduced to about several tens of ⁇ .
  • the lead frame is hermetically sealed with resin to obtain a
  • the lead frame is also hermetically sealed with resin to obtain a semiconductor device product.
  • a TAB tape includes a plurality of leads which are made of
  • An object of the present invention is to provide a lead frame and a semiconductor device using the same lead f rame, in which the lead frame can be easily handled, as if it was a lead frame using a TAB tape or thin material, so that a semiconductor device product using such a lead frame can easily be mounted on a printed circuit board.
  • a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily f orming af ine pattern of said inner leads; and a
  • a semiconductor device comprising: (a) a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily forming af ine pattern of said inner leads; and a plurality of outer leads formed formed with said respective inner leads, said outer leads being coated with metal layers to increase the thickness thereof, so that a desired strength of said outer leads is obtained; (b) a semiconductor chip electrically connected to said inner leads; and (c) a resin for hermetically sealing said semiconductor chip and a part of said lead f rame including said inner leads.
  • a semiconductor device comprising: (a) a lead frame comprising: an insulating base f ilm having a device hole at a central position thereof and window holes located apart from said device hole; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads formed formed with said respective inner leads, so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness that, so that a desired strength of said outer leads is obtained; (b) a semiconductor chip mounted on and electrically connected to said inner leads within said central opening; and (c) a resin for hermetically sealing said semiconductor chip and a part of said lead frame
  • a semiconductor device comprising :( a) a lead frame comprising: an insulating base film having window holes located apart from a central position of said base film; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads, formed with said respective inner leads, so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window- hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness thereof, so that a desired
  • FIGS. 1A-ID are plan views of some embodiments of a lead frame according to the present invention.
  • Figures 2A-2D are plan views of embodiments of a semiconductor device using a lead frame shown in
  • Figure 3 is a cross-sectional view of a
  • Figure 4 is a cross-sectional view of a
  • Figures 5A-5C are cross-sectional views of some variations of a lead frame according to the present invention.
  • Figures 6A-6D are cross-sectional views of some variations of an inner lead-bonding type semiconductor device according to the present invention.
  • Figure 7 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device according to the present invention.
  • Figure 8 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device according to the present invention.
  • Figures 9A-9D are cross -sectional views of some variations of a potted type semiconductor device
  • Figure 10 is a cross-sectional view of another embodiment of a potted type semiconductor device
  • Figure 11 is a cross -sectional view of an embodiment of an inner lead-bonding type semiconductor device having a heat spreader or heat sink;
  • Figure 12 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device having a heat spreader
  • Figure 13 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device having a heat spreader.
  • Figs .1A ID are plan views of some embodiments of a lead frame composed as a TAB tape according to the present invention .
  • the TAB tape s an electrically insulating flexible base film 10, made of a material such as a polyimide, and an electrically conductive pattern formed on a surface of the base film .
  • the conductive pattern having a desired pattern can be formed by any consistent known method, such as by etching the conductive thin film attached on the base film 10. Any known method can be used, such as a sputtering, vapor deposition, or adhering a copper foil onto the base film using any suitable adhesive.
  • the base film 10 of the (inner lead bonding type) TAB tapes shown in Figs .1A and IB is first provided with a device hole 12 at the central position of the TAB tape, four window holes 14 located apart from the device hole and symmetrically arranged to each other, and sprocket holes 16 equidistant ly and regularly arranged at the edges of the TAB tape .
  • a copper foil is then adhered to the base film 10 and etched to obtain a desired
  • the conductive pattern insulating inner leads 18 having the respective inner tips extending inward to the inside of the device hole 12 and the corresponding outer leads 20 extending outward from the respective inner leads 18 and over the window holes 14,
  • the outer leads 20 are cut at the outer edge of the window holes 14,, as shown line P in Fig, lA f after a semiconductor chip (not shown) is mounted on the TAB tape and hermetically sealed with resin (not shown).
  • the (wire-bonding type) TAB tape shown in Figs .1C and ID is substantially the same as the TAB tape shown in Figs .1A and IB, except that the base film 10 has no central device hole, but a conductive die pad 28 is formed at the central position of the TAB tape, Such a conductive die pad 28 can be formed simultaneously with the conductive pattern comprising inner and outer leads 18 and 20 *
  • tie bar 20a is provided for continuously connecting the outer leads.
  • tie bar 20a can also be formed simultaneously with the conductive pattern comprising inner and outer
  • tie bars 20a are cut out to separate the adjacent outer leads 20 from each other, as shown lines Q in Figs ⁇ IB and ID, after a semiconductor chip (not shown) is mounted on the TAB tape and
  • FIGs 2A-2D semiconductor devices using lead frames of Figs 1A -. ID, respectively r are shown
  • Fig -.. 3 is a cross -sectional view of the (inner lead bonding type) TAB tape shown semiconductor device of Fig 2A or 2B .
  • Fig. 4 is a cross-sectional view of the (wire-bonding type) semiconductor device of Fig. 2C or 2D.
  • the conductive part of the outer lead is increased, in such a manner that the outer lead has a thickness substantially the same as the outer lead of a conventional met l lead frame-resulting, in the embodiment of this
  • the foil is etched to obtain a desired
  • the width of the outer lead 20 can also be
  • the thickness of the inner leads 18 i.e., the thickness of the copper foil
  • the thickness of the outer leads 20 can be thus increased to about 125 ⁇ .
  • solder resist 22 is coated on the inner leads 18 at a position of the inner leads 18 corresponding to a clamp position of a mold (not shown) which is used, at a later stage, for hermetically sealing the semiconductor device with a resin 26, in such a manner that the gaps between the adjacent inner leads 18 are filled with the resist to prevent the sealing
  • the semiconductor chip 24 is mounted on the TAB tapes, in such a manner that the s emi conductor chip 24 is connected to the inner leads 18 by a simultaneous bonding via bumps 18a provided on the surfaces of the semiconductor chip 24. Then, the TAB tape is clamped by the mold (not shown) in the direction of thickness between the base film 10 and solder resist 22 and a resin 26 is then filled in the mold to obtain a hermetically sealed semiconductor device.
  • a wire-bonding type TAB tape the die pad 28 and the inner leads 18 are mutually supported by the base film portion 30, which maintains the micro-pattern of inner leads 18 to prevent any movement thereof .
  • a semiconductor chip 24 is mounted on the die pad 28 of the TAB tape and, then, the t
  • the outer leads 20 can be prevented from being easily deformed or bent.
  • Fig. 7 is a cross -sectional view of a wire-bonding type semiconductor device, in which the semiconductor chip 24 is mounted on the lower surface of the die pad 28 and connected to the inner leads 18 by the bonding wires 18b through the second window holes 14a, as
  • Fig, 7 shows an embodiment in which the solder resist 22 is coated on the inner
  • solder resist 22 can be coated after the copper-plating as the embodiment of Fig, 6B, or such a solder resist 22 may either be coated before or after the copper-plating, as the
  • Fig. 8 is a cross-sectional view of another wire- bonding type semiconductor device, in which the
  • solder resist 22 is coated on the inner leads 18 before the copper- plating, in the same manner as the embodiment of Fig, 6A, such a solder resist 22 can be coated after the copper- plating as the embodiment of Fig .6B, or either before or af ter the copper-plating as the embodiment of Fig .6C .Also, there may be no such solder resist (22) as the embodiment of Fig .6D.
  • insulating base f ilm 10 made of such as a polyimide, is replaced by a metal plate, the conductive pattern
  • Fig .12 (wire-bonding type) is substantially the same as the embodiment of Fig .7, except that a heat spreader 34 is disposed in the same manner as the embodiment of Fig .12 ⁇
  • spreader 34 in this embodiment isolated a central convex portion which contacts the die-pad 28 opposite the semiconductor chip 24, an intermediate upper portion exposed to the outside, and a peripheral portion which contacts the solder resist 22 ⁇
  • Fig .13 is substantially the same as the embodiment of Fig .8, except that a heat spreader 34 is disposed in the same manner as the above-mentioned embodiments ⁇
  • the heat spreader 34 in this embodiment cross a central convex portion which contacts the base f ilm 10 opposite the die- pad 28 and the semiconductor chip 24, an intermediate bottom portion exposed to the outside, and a peripheral portion which also contacts the same base film 10
  • a metal plate made of copper or 42% copper alloy with an electrically insulating layer on the surface thereof is used as a base film .However, such a base film of metal plate can also be used in the embodiments other than those of Figs .8 and 10.
  • the lead frame can be made in accordance with a similar process for making a TAB tape, in which a copper foil is f irst formed on a base insulating f ilm and then a conductive pattern is formed by etching the copper foil .
  • the lead frame can also be made in accordance with a process in which a lead pattern is f irst formed and then the lead pattern is supported by an insulating film .
  • the lead frame thus made can be used to mount a semiconductor chip thereon and can be handled in the same manner as a conventional lead f rame, A semiconductor device product sealed with a resin can also be easily- handled,
  • "lead frame" used for mounting thereon a semiconductor chip is also referred to as "TAB tape"
  • the outer leads can be plated partially with copper, in the embodiments as mentioned above .However, in practice, the following methods can be employed, in consideration of the bonding characteristic at the inner lead portions and the mounting characteristic at the outer lead portions .In any case, copper can be used as a base material to increase the thickness of the outer leads.
  • the outer leads are plated with copper or solder to increase the thickness that .
  • the entire lead surfaces including inner and outer leads are plated with nickel as an under layer, then all of the leads are plated with a gold, and then only the outer lead portions are subjected to plating to increase the thickness agree-In this case, to increase the thickness, 'the outer leads may be plated with copper r plated with solder after plated with copper, or plated with solder in place of copper ⁇ Thus r the portions of the outer leads plated with copper or solder, which is exposed to the outside.
  • Both inner and outer leads are plated with palladium to form protective layers .
  • all the lead surfaces, including inner and outer leads are plated with palladium .
  • the copper foil is plated with nickel as an underlayer
  • the outer lead portions are subjected to plating to increase the thickness that, and then the entire lead surface including inner and outer leads are plated with palladium-In this case, after the outer lead portions are plated with copper to increase the thickness thereof, solder may further be plated thereon.
  • Both inner and outer leads are plated with tin to form a protective layer .
  • tin can be plated directly on the copper material without an underlayer, only the outer lead portions are first plated with a copper or solder to increase the thickness
  • the outer lead portions may be first plated with copper and then plated with solder to increase the thickness thereof and then the entire lead surface including inner and outer leads may be plated with tin.
  • the thickness of the inner leads can be any thickness of the inner leads.
  • this method is particularly suitable for making a TAB tape having fine patterns
  • the thickness of the plated layer can advantageous ly be selected in such a manner that the thickness of the plated gold is 0, 3 to 5 ⁇ , the thickness of the plated nickel is 1 to 20 ⁇ / the thickness of the plated palladium is 0 .1 to 0.5 ⁇ , and the thickness of the plated tin is about 0 .5 ⁇ .
  • the thickness of the plated layer for increasing the thickness of the outer leads may be 50 to 70 ⁇ .
  • the base copper material has a thickness of about several tens of ⁇ ⁇ the entire thickness of the outer lead including the plated underlayer or the like may thus be about ⁇ .
  • the outer leads are subjected to plating to increase the thickness that, the thickness of the outer leads 20 may be increased by any other method, such as sputtering, vapor deposition, or the like method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Dans un cadre de montage destiné à être utilisé pour un composant à semi-conducteurs, une pluralité de fils intérieurs (18) sont constitués d'un matériau conducteur mince permettant la formation aisée d'un motif fin des fils intérieurs. Une pluralité de fils extérieurs (20) sont formés d'une seule pièce avec les fils intérieurs respectifs. Les fils extérieurs sont revêtus de couches métalliques pour augmenter leur épaisseur, ce qui permet d'obtenir la résistance souhaitée des fils extérieurs. Une puce (24) est connectée électriquement aux fils intérieurs. Cette puce et une partie du cadre de montage comprenant les fils intérieurs sont scellées hermétiquement avec une résine (26) et, ainsi, on obtient un composant à semi-conducteurs.In a mounting frame for use with a semiconductor component, a plurality of interior wires (18) are made of a thin conductive material allowing easy formation of a fine pattern of the interior wires. A plurality of outer wires (20) are integrally formed with the respective inner wires. The outer wires are coated with metallic layers to increase their thickness, which makes it possible to obtain the desired resistance of the outer wires. A chip (24) is electrically connected to the interior wires. This chip and part of the mounting frame comprising the inner wires are hermetically sealed with a resin (26) and, thus, a semiconductor component is obtained.

Description

DESCRIPTION  DESCRIPTION

Lead Frame and Semiconductor Device Using Same Lead Frame and Semiconductor Device Using Same

TECHNICAL FIELD  TECHNICAL FIELD

The present invention relates to a lead frame and a semiconductor device using the same lead frame . This invention also relates to a process for making such a lead frame .  The present invention relates to a lead frame and a semiconductor device using the same lead frame .This invention also relates to a process for making such a lead frame.

BACKGROUND ART  BACKGROUND ART

In the field of lead frames adapted to be used for a semiconductor device , since semiconductor chips have become highly integrated , multi-pin lead frames having a large nxunber of leads and a fine lead pattern structure have been developed and produced . In this connection , in order to make a fine lead pattern structure on a lead frame , a relatively thin material has been used as a lead frame base and an etching process has been widely adopted to form such fine micro-patterns , since the etching process is more suitable than the other processes , such as a punching process , to easily form such fine patterns .  In the field of lead frames adapted to be used for a semiconductor device, since semiconductor chips have become highly integrated, multi-pin lead frames having a large nxunber of leads and a fine lead pattern structure have been developed and produced .In this connection, in order to make a fine lead pattern structure on a lead frame, a relatively thin material has been used as a lead frame base and an etching process has been widely adopted to form such fine micro-patterns, since the etching process is more suitable than the other processes, such as a punching process, to easily form such fine patterns.

In a conventional method for manufacturing a lead frame , however , there has been a limitation on forming a very fine lead pattern . Thus , a TAB ( tape automated bonding ) tape lead frame has been developed and used , on which a finer pattern could be formed than on a  In a conventional method for manufacturing a lead frame, however, there has been a limitation on forming a very fine lead pattern .So, a TAB (tape automated bonding) tape lead frame has been developed and used, on which a finer pattern could be formed than on a

conventional metal lead frame . conventional metal lead frame.

A TAB tape can be made by forming a thin conductive film on an electrically insulative base film and etching the conductive film to form a desired conductive pattern . Using such a TAB tape , since the conductive patterns are supported on a thin f lexible base film, the thickness of such conductive patterns can be reduced to about several tens of μπι . Thus , it becomes possible to make very fine patterns of leads which could not be attained on a conventional metal lead frame .  A TAB tape can be made by forming a thin conductive film on an electrically insulative base film and etching the conductive film to form a desired conductive pattern .Using such a TAB tape, since the conductive patterns are supported on a thin f lexible base film, the thickness of such conductive patterns can be reduced to about several tens of μπι. Thus, it becomes possible to make very fine patterns of leads which could not be achieved on a conventional metal lead frame.

On the other hand , a semiconductor device is  On the other hand, a semiconductor device is

conventionally made as follows . After the inner leads of the lead frame are electrically connected to the after made as follows .After the inner leads of the lead frame are electrically connected to the

semiconductor chip by a wire-bonding process , the lead frame is hermetically sealed with resin to obtain a semiconductor chip by a wire-bonding process, the lead frame is hermetically sealed with resin to obtain a

product♦ In a case where a TAB tape is used , the lead frame is also hermetically sealed with resin to obtain a semiconductor device product . product ♦ In a case where a TAB tape is used, the lead frame is also hermetically sealed with resin to obtain a semiconductor device product.

However , as mentioned above , since a TAB tape includes a plurality of leads which are made of  However, as mentioned above, since a TAB tape includes a plurality of leads which are made of

conductive thin film , there has been a problem that a strength of leads are not suf f icient and it is dif f icult to handle the same , such as when the product is mounted on a printed circuit board . conductive thin film, there has been a problem that a strength of leads are not suf f icient and it is dif f icult to handle the same, such as when the product is mounted on a printed circuit board.

The above-mentioned problems concerning a TAB— tape also appear when a so-called single-layer-type TAB tape is used to make a lead frame , in which the leads are formed of a very thin conductive material with a  The above-mentioned problems concerning a TAB— tape also appear when a so-called single-layer-type TAB tape is used to make a lead frame, in which the leads are formed of a very thin conductive material with a

thickness of not more than Ι ΟΟμπι . thickness of not more than Ι ΟΟμπι.

In addition , after the leads have been formed , it is necessary to prevent the leads from being deformed or bent . Thus f it becomes necessary that the outer leads have a certain strength to stably and accurately mount the product on a printed circuit board without any deformation of the leads , In addition, after the leads have been formed, it is necessary to prevent the leads from being deformed or bent .So f it becomes necessary that the outer leads have a certain strength to stably and accurately mount the product on a printed circuit board without any deformation of the leads,

DISCL SURE OF INVENTION  DISCL SURE OF INVENTION

An object of the present invention is to provide a lead frame and a semiconductor device using the same lead f rame , in which the lead frame can be easily handled , as if it was a lead frame using a TAB tape or thin material , so that a semiconductor device product using such a lead frame can easily be mounted on a printed circuit board .  An object of the present invention is to provide a lead frame and a semiconductor device using the same lead f rame, in which the lead frame can be easily handled, as if it was a lead frame using a TAB tape or thin material, so that a semiconductor device product using such a lead frame can easily be mounted on a printed circuit board.

According to one aspect of the present invention , there is provided a lead frame adapted to be used for a semiconductor device comprising : a plurality of inner leads made of a thin conductive material for easily f orming a f ine pattern of said inner leads； and a  According to one aspect of the present invention, there is provided a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily f orming af ine pattern of said inner leads; and a

plurality of outer leads integrally formed with said respective inner leads , said outer leads being coated plurality of outer leads together formed with said respective inner leads, said outer leads being coated

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According to still further aspect of the present invention f there is provided a process for making a lead frame adapted to be used for a semiconductor device : According to still further aspect of the present invention f there is provided a process for making a lead frame adapted to be used for a semiconductor device:

comprising the following steps of： forming a conductive layer on an insulating base f ilm having window holes located apart from a central position of said base f ilm; etching said conductive layer to form a conductive pattern including a die - pad located at a central position of said insulating base f ilm, a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole ; and coating said outer leads with metal layers to increase the thickness thereof , so that a desired strength of said outer leads is obtained . comprising the following steps of: forming a conductive layer on an insulating base f ilm having window holes located apart from a central position of said base f ilm; etching said conductive layer to form a conductive pattern including a die-pad located at a central position of said insulating base f ilm, a plurality of inner leads and a plurality of outer leads formed formed with said respective inner leads, so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole; and coating said outer leads with metal layers to increase the thickness thereof, so that a desired strength of said outer leads is obtained.

According to still another aspect of the present invention , there is provided a semiconductor device comprising： ( a ) a lead frame adapted to be used for a semiconductor device comprising : a plurality of inner leads made of a thin conductive material for easily forming a f ine pattern of said inner leads； and a plurality of outer leads integrally formed with said respective inner leads , said outer leads being coated with metal layers to increase the thickness thereof , so that a desired strength of said outer leads is obtained ; ( b ) a semiconductor chip electrically connected to said inner leads； and ( c ) a resin for hermetically sealing said semiconductor chip and a part of said lead f rame including said inner leads .  According to still another aspect of the present invention, there is provided a semiconductor device comprising: (a) a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily forming af ine pattern of said inner leads; and a plurality of outer leads formed formed with said respective inner leads, said outer leads being coated with metal layers to increase the thickness thereof, so that a desired strength of said outer leads is obtained; (b) a semiconductor chip electrically connected to said inner leads; and (c) a resin for hermetically sealing said semiconductor chip and a part of said lead f rame including said inner leads.

According to still another aspect of the present invention , there is provided a semiconductor device comprising： ( a ) a lead frame comprising： an insulating base f ilm having a device hole at a central position thereof and window holes located apart from said device hole ; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole ; and said inner leads being relatively thin , but said outer leads being coated with metal layers to increase the thickness thereof , so that a desired strength of said outer leads is obtained ; ( b ) a semiconductor chip mounted on and electrically connected to said inner leads within said central opening； and ( c ) a resin for hermetically sealing said semiconductor chip and a part of said lead frame According to still another aspect of the present invention, there is provided a semiconductor device comprising: (a) a lead frame comprising: an insulating base f ilm having a device hole at a central position thereof and window holes located apart from said device hole; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads formed formed with said respective inner leads, so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness that, so that a desired strength of said outer leads is obtained; (b) a semiconductor chip mounted on and electrically connected to said inner leads within said central opening; and (c) a resin for hermetically sealing said semiconductor chip and a part of said lead frame

including said inner leads . including said inner leads.

According to still another aspect of the present invention , there is provided a semiconductor device comprising : ( a ) a lead frame comprising : an insulating base film having window holes located apart from a central position of said base film; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window- hole ; and said inner leads being relatively thin , but said outer leads being coated with metal layers to increase the thickness thereof , so that a desired  According to still another aspect of the present invention, there is provided a semiconductor device comprising :( a) a lead frame comprising: an insulating base film having window holes located apart from a central position of said base film; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads, formed with said respective inner leads, so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window- hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness thereof, so that a desired

strength of said outer leads is obtained; ( b ) a strength of said outer leads is obtained; (b) a

semiconductor chip mounted on said die-pad ; ( c ) bonding wires for electrically connecting said semiconductor chip to said inner leads； and (d ) a resin for hermetically sealing said semiconductor chip and a part of said lead frame including said inner leads . semiconductor chip mounted on said die-pad; (c) bonding wires for electrically connecting said semiconductor chip to said inner leads; and (d) a resin for hermetically sealing said semiconductor chip and a part of said lead frame including said inner leads.

BRIEF DESCRIPTION OF DRAWINGS Figures 1A - ID are plan views of some embodiments of a lead frame according to the present invention ; BRIEF DESCRIPTION OF BRIEF Figures 1A-ID are plan views of some embodiments of a lead frame according to the present invention;

Figures 2A - 2D are plan views of embodiments of a semiconductor device using a lead frame shown in  Figures 2A-2D are plan views of embodiments of a semiconductor device using a lead frame shown in

Figs . 1A - ID, respectively, according to the present invention ; Figs .1A-ID, respectively, according to the present invention;

Figure 3 is a cross-sectional view of a  Figure 3 is a cross-sectional view of a

semiconductor device shown in Fig . 2A or 2B ; semiconductor device shown in Fig .2A or 2B;

Figure 4 is a cross-sectional view of a  Figure 4 is a cross-sectional view of a

semiconductor device shown in Fig . 2C or 2D; semiconductor device shown in Fig .2C or 2D;

Figures 5A-5C are cross - sectional views of some variations of a lead frame according to the present invention ;  Figures 5A-5C are cross-sectional views of some variations of a lead frame according to the present invention;

Figures 6A-6D are cross-sectional views of some variations of an inner lead-bonding type semiconductor device according to the present invention ;  Figures 6A-6D are cross-sectional views of some variations of an inner lead-bonding type semiconductor device according to the present invention;

Figure 7 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device according to the present invention；  Figure 7 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device according to the present invention;

Figure 8 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device according to the present invention ;  Figure 8 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device according to the present invention;

Figures 9A-9D are cross -sectional views of some variations of a potted type semiconductor device ;  Figures 9A-9D are cross -sectional views of some variations of a potted type semiconductor device;

Figure 10 is a cross-sectional view of another embodiment of a potted type semiconductor device ;  Figure 10 is a cross-sectional view of another embodiment of a potted type semiconductor device;

Figure 11 is a cross -sectional view of an embodiment of an inner lead-bonding type semiconductor device having a heat spreader or heat sink ;  Figure 11 is a cross -sectional view of an embodiment of an inner lead-bonding type semiconductor device having a heat spreader or heat sink;

Figure 12 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device having a heat spreader; and  Figure 12 is a cross-sectional view of an embodiment of a wire-bonding type semiconductor device having a heat spreader; and

Figure 13 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device having a heat spreader .  Figure 13 is a cross-sectional view of another embodiment of a wire-bonding type semiconductor device having a heat spreader.

BEST MODE FOR CARRYING OUT THE INVENTION  BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to the drawings , wherein Figs . 1A— ID are plan views of some embodiments of a lead frame constituted as a TAB tape according to the present invention . The TAB tape comprises an electrically insulating flexible base film 10 , made of a material such as a polyimide , and an electrically conductive pattern formed on a surface of the base film . The conductive pattern having a desired pattern can be formed by any conventionally known method , such as by etching the conductive thin film attached on the base film 10 . In order to attach a thin conductive film onto the base film, any known method can be used , such as a sputtering , vapor deposition , or adhering a copper foil onto the base film using any suitable adhesive . Referring now to the drawings, where Figs .1A— ID are plan views of some embodiments of a lead frame composed as a TAB tape according to the present invention .The TAB tapes an electrically insulating flexible base film 10, made of a material such as a polyimide, and an electrically conductive pattern formed on a surface of the base film .The conductive pattern having a desired pattern can be formed by any consistent known method, such as by etching the conductive thin film attached on the base film 10. any known method can be used, such as a sputtering, vapor deposition, or adhering a copper foil onto the base film using any suitable adhesive.

The base film 10 of the ( inner lead bonding type ) TAB tapes shown in Figs . 1A and IB is first provided with a device hole 12 at the central position of the TAB tape , four window holes 14 located apart from the device hole and symmetrically arranged to each other , and sprocket holes 16 equidistant ly and regularly arranged at the edges of the TAB tape . A copper foil is then adhered to the base film 10 and etched to obtain a desired  The base film 10 of the (inner lead bonding type) TAB tapes shown in Figs .1A and IB is first provided with a device hole 12 at the central position of the TAB tape, four window holes 14 located apart from the device hole and symmetrically arranged to each other, and sprocket holes 16 equidistant ly and regularly arranged at the edges of the TAB tape .A copper foil is then adhered to the base film 10 and etched to obtain a desired

conductive pattern . The conductive pattern comprises inner leads 18 having the respective inner tips extending inward to the inside of the device hole 12 and the corresponding outer leads 20 extending outward from the respective inner leads 18 and over the window holes 14 , The outer leads 20 are cut at the outer edge of the window holes 14 , as shown line P in Fig , lAf after a semiconductor chip ( not shown ) is mounted on the TAB tape and hermetically sealed with resin ( not shown ) . conductive pattern .The conductive pattern insulating inner leads 18 having the respective inner tips extending inward to the inside of the device hole 12 and the corresponding outer leads 20 extending outward from the respective inner leads 18 and over the window holes 14, The outer leads 20 are cut at the outer edge of the window holes 14,, as shown line P in Fig, lA f after a semiconductor chip (not shown) is mounted on the TAB tape and hermetically sealed with resin (not shown).

The (wire-bonding type ) TAB tape shown in Figs . 1C and ID is substantially the same as the TAB tape shown in Figs . 1A and IB , except that the base film 10 has no central device hole , but a conductive die pad 28 is formed at the central position of the TAB tape , Such a conductive die pad 28 can be formed simultaneously with the conductive pattern comprising inner and outer leads 18 and 20 * The (wire-bonding type) TAB tape shown in Figs .1C and ID is substantially the same as the TAB tape shown in Figs .1A and IB, except that the base film 10 has no central device hole, but a conductive die pad 28 is formed at the central position of the TAB tape, Such a conductive die pad 28 can be formed simultaneously with the conductive pattern comprising inner and outer leads 18 and 20 *

The TAB tapes shown in Figs . IB and ID are  The TAB tapes shown in Figs .IB and ID are

substantially the same as the TAB tapes shown in Figs . 1A and 1C , respectively, except that a tie bar 20a is provided for continuously connecting the outer leads .substantially the same as the TAB tapes shown in Figs. 1A and 1C, respectively, except that a tie bar 20a is provided for continuously connecting the outer leads.

Such a tie bar 20a can also be formed simultaneously with the conductive pattern comprising inner and outer Such a tie bar 20a can also be formed simultaneously with the conductive pattern comprising inner and outer

leads 18 and 20 · Also , these tie bars 20a are cut out to separate the adjacent outer leads 20 from each other , as shown lines Q in Figs · IB and ID , after a semiconductor chip ( not shown ) is mounted on the TAB tape and leads 18 and 20 ・ Also, these tie bars 20a are cut out to separate the adjacent outer leads 20 from each other, as shown lines Q in Figs ・ IB and ID, after a semiconductor chip (not shown) is mounted on the TAB tape and

hermetically sealed with resin ( not shown ) . hermetically sealed with resin (not shown).

In Figs . 2A-2D , semiconductor devices using lead frames of Figs . 1A - ID , respectively r are shown . Fig - 3 is a cross -sectional view of the ( inner lead bonding type ) TAB tape shown semiconductor device of Fig . 2A or 2B . Fig . 4 is a cross - sectional view of the (wire - bonding type ) semiconductor device of Fig . 2C or 2D . . In Figs 2A-2D, semiconductor devices using lead frames of Figs 1A -. ID, respectively r are shown Fig -.. 3 is a cross -sectional view of the (inner lead bonding type) TAB tape shown semiconductor device of Fig 2A or 2B .Fig. 4 is a cross-sectional view of the (wire-bonding type) semiconductor device of Fig. 2C or 2D.

In each type of TAB tapes , the thickness of  In each type of TAB tapes, the thickness of

conductive part of the outer lead is increased , in such a manner that the outer lead has a thickness substantially the same as the outer lead of a conventional met l lead frame - Consequently , in the embodiment of this conductive part of the outer lead is increased, in such a manner that the outer lead has a thickness substantially the same as the outer lead of a conventional met l lead frame-resulting, in the embodiment of this

invention , after the copper foil is adhered to the base film 10 , the foil is etched to obtain a desired invention, after the copper foil is adhered to the base film 10, the foil is etched to obtain a desired

conductive pattern comprising inner leads 18 and the corresponding outer leads 20 and then a nickel is plated , in the same manner as a conventional method . Then , a copper is further plated only on the outer lead conductive pattern comprising inner leads 18 and the corresponding outer leads 20 and then a nickel is plated, in the same manner as a conventional method .Then, a copper is further plated only on the outer lead

portions 20 to increase the thickness thereof . As the thickness of the outer leads 20 are increased , as shown in Figs . 3 and 4 , by the copper-plating r the strength can also be increased to substantially the same level as a conventional metal lead frame . portions 20 to increase the thickness that .As the thickness of the outer leads 20 are increased, as shown in Figs .3 and 4, by the copper-plating r the strength can also be increased to substantially the same level as a conventional metal lead frame.

The width of the outer lead 20 can also be  The width of the outer lead 20 can also be

increased , as well as the thickness thereof by the above- mentioned copper - platinq · However , since the gaps between the adjacent outer leads 20 are much larger than the gaps between the adjacent inner leads 18, it is effective to plate the cuter leads 20 with a copper to increase the thickness of the outer leads 20 to a certain value so as to increase the strength thereof . increased, as well as the thickness thereof by the above- mentioned copper-platinq · However, since the gaps between the adjacent outer leads 20 are much larger than the gaps between the adjacent inner leads 18, it is effective to plate the cuter leads 20 with a copper to increase the thickness of the outer leads 20 to a certain value so as to increase the strength that.

In a typical TAB tape, in practice, where the thickness of the inner leads 18 (i.e. , the thickness of the copper foil ) is about 12 - 70μπ, the thickness of the outer leads 20 can be thus increased to about 125μπι.  In a typical TAB tape, in practice, where the thickness of the inner leads 18 (i.e., the thickness of the copper foil) is about 12-70 μπ, the thickness of the outer leads 20 can be thus increased to about 125 μπι.

As clearly shown in Figs · 2A, 2B, 3 and 4 r a As clearly shown in Figs · 2A, 2B, 3 and 4 r a

rectangular or frame-shaped solder resist 22 is coated on the inner leads 18 at a position of the inner leads 18 corresponding to a clamp position of a mold (not shown) which is used, at a later stage, for hermetically sealing the semiconductor device with a resin 26, in such a manner that the gaps between the adjacent inner leads 18 are filled with the resist to prevent the sealing rectangular or frame-shaped solder resist 22 is coated on the inner leads 18 at a position of the inner leads 18 corresponding to a clamp position of a mold (not shown) which is used, at a later stage, for hermetically sealing the semiconductor device with a resin 26, in such a manner that the gaps between the adjacent inner leads 18 are filled with the resist to prevent the sealing

resin 26 from flowing out of the mold (not shown) , during a molding process . resin 26 from flowing out of the mold (not shown), during a molding process.

In the TAB tapes shown in Figs . 2A, 2B and 3 (i.e., inner lead bonding type TAB tapes), the semiconductor chip 24 is mounted on the TAB tapes, in such a manner that the s emi conductor chip 24 is connected to the inner leads 18 by a simultaneous bonding via bumps 18a provided on the surfaces of the semiconductor chip 24. Then, the TAB tape is clamped by the mold (not shown) in the direction of thickness between the base film 10 and solder resist 22 and a resin 26 is then filled in the mold to obtain a hermetically sealed semiconductor device .  In the TAB tapes shown in Figs. 2A, 2B and 3 (ie, inner lead bonding type TAB tapes), the semiconductor chip 24 is mounted on the TAB tapes, in such a manner that the s emi conductor chip 24 is connected to the inner leads 18 by a simultaneous bonding via bumps 18a provided on the surfaces of the semiconductor chip 24. Then, the TAB tape is clamped by the mold (not shown) in the direction of thickness between the base film 10 and solder resist 22 and a resin 26 is then filled in the mold to obtain a hermetically sealed semiconductor device.

On the other hand, in the TAB tape shown in  On the other hand, in the TAB tape shown in

Figs . 2C, 2D and 41 i.e., a wire-bonding type TAB tape, the die pad 28 and the inner leads 18 are mutually supported by the base film portion 30, which maintains the micro-pattern of inner leads 18 to prevent any movement thereof . A semiconductor chip 24 is mounted on the die pad 28 of the TAB tape and, then, the t Figs .2C, 2D and 4 1 ie, a wire-bonding type TAB tape, the die pad 28 and the inner leads 18 are mutually supported by the base film portion 30, which maintains the micro-pattern of inner leads 18 to prevent any movement thereof .A semiconductor chip 24 is mounted on the die pad 28 of the TAB tape and, then, the t

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therefore , the outer leads 20 can be prevented from being easily deformed or bent . therefore, the outer leads 20 can be prevented from being easily deformed or bent.

Fig . 7 is a cross -sectional view of a wire-bonding type semiconductor device , in which the semiconductor chip 24 is mounted on the lower surface of the die pad 28 and connected to the inner leads 18 by the bonding wires 18b through the second window holes 14a , as  Fig. 7 is a cross -sectional view of a wire-bonding type semiconductor device, in which the semiconductor chip 24 is mounted on the lower surface of the die pad 28 and connected to the inner leads 18 by the bonding wires 18b through the second window holes 14a, as

mentioned above with reference to Fig , 5C . Regarding the solder resist 22 , although Fig , 7 shows an embodiment in which the solder resist 22 is coated on the inner mentioned above with reference to Fig, 5C .Regarding the solder resist 22, although Fig, 7 shows an embodiment in which the solder resist 22 is coated on the inner

leads 18 bef ore the thickness of the outer leads 20 is increased by a copper-platinq , in the same manner as the embodiment of Fig . 6A . However , such a solder resist 22 can be coated after the copper-plating as the embodiment of Fig , 6B , or such a solder resist 22 may either be coated before or after the copper-plating , as the leads 18 bef ore the thickness of the outer leads 20 is increased by a copper-platinq, in the same manner as the embodiment of Fig .6A .However, such a solder resist 22 can be coated after the copper-plating as the embodiment of Fig, 6B, or such a solder resist 22 may either be coated before or after the copper-plating, as the

embodiment of Fig . 6C . Also , there may be no such solder resist ( 22 ) as the embodiment of Fig , 6D . embodiment of Fig .6C .Also, there may be no such solder resist (22) as the embodiment of Fig, 6D.

Fig . 8 is a cross-sectional view of another wire- bonding type semiconductor device , in which the  Fig. 8 is a cross-sectional view of another wire- bonding type semiconductor device, in which the

semiconductor chip 24 is mounted on the upper surface of the die pad 28 of the TAB tape as shown in Fig . 5B and connected to the inner leads 18 by the bonding wires 18b . Also , in this embodiment , although the solder resist 22 is coated on the inner leads 18 before the copper- plating , in the same manner as the embodiment of Fig , 6A, such a solder resist 22 can be coated after the copper- plating as the embodiment of Fig . 6B , or either before or af ter the copper-plating as the embodiment of Fig . 6C . Also , there may be no such solder resist ( 22 ) as the embodiment of Fig . 6D . semiconductor chip 24 is mounted on the upper surface of the die pad 28 of the TAB tape as shown in Fig .5B and connected to the inner leads 18 by the bonding wires 18b .Also, in this embodiment, although the solder resist 22 is coated on the inner leads 18 before the copper- plating, in the same manner as the embodiment of Fig, 6A, such a solder resist 22 can be coated after the copper- plating as the embodiment of Fig .6B, or either before or af ter the copper-plating as the embodiment of Fig .6C .Also, there may be no such solder resist (22) as the embodiment of Fig .6D.

In the embodiment of Fig - 8 , if the f lexible  In the embodiment of Fig-8,, if the f lexible

insulating base f ilm 10 , made of such as a polyimide , is replaced by a metal plate , the conductive pattern insulating base f ilm 10, made of such as a polyimide, is replaced by a metal plate, the conductive pattern

including the die-pad 28 and inner and outer leads 18 and 22 are formed on the metal plate ( 10 ) via an electrically C O including the die-pad 28 and inner and outer leads 18 and 22 are formed on the metal plate (10) via an electrically CO

o o o  o o o

and a peripheral portion contacts the base film 10 ·and a peripheral portion contacts the base film 10

The embodiment of Fig . 12 ( wire-bonding type ) is substantially the same as the embodiment of Fig . 7 , except that a heat spreader 34 is disposed in the same manner as the embodiment of Fig . 12 · The heat The embodiment of Fig .12 (wire-bonding type) is substantially the same as the embodiment of Fig .7, except that a heat spreader 34 is disposed in the same manner as the embodiment of Fig .12 · The heat

spreader 34 in this embodiment comprises a central convex portion which contacts the die-pad 28 opposite the semiconductor chip 24 , an intermediate upper portion exposed to the outside , and a peripheral portion which contacts the solder resist 22 · spreader 34 in this embodiment isolated a central convex portion which contacts the die-pad 28 opposite the semiconductor chip 24, an intermediate upper portion exposed to the outside, and a peripheral portion which contacts the solder resist 22 ・

The embodiment of Fig . 13 ( another wire-bonding type ) is substantially the same as the embodiment of Fig . 8 , except that a heat spreader 34 is disposed in the same manner as the above-mentioned embodiments · The heat spreader 34 in this embodiment comprises a central convex portion which contacts the base f ilm 10 opposite the die- pad 28 and the semiconductor chip 24 , an intermediate bottom portion exposed to the outside , and a peripheral portion which also contacts the same base film 10 ·  The embodiment of Fig .13 (another wire-bonding type) is substantially the same as the embodiment of Fig .8, except that a heat spreader 34 is disposed in the same manner as the above-mentioned embodiments · The heat spreader 34 in this embodiment cross a central convex portion which contacts the base f ilm 10 opposite the die- pad 28 and the semiconductor chip 24, an intermediate bottom portion exposed to the outside, and a peripheral portion which also contacts the same base film 10

In the embodiments of Figs . 8 and 10 , instead of an insulating base film made of polyimide , a metal plate made of copper or 42% copper alloy with an electrically insulating layer on the surface thereof is used as a base film . However , such a base film of metal plate can also be used in the embodiments other than those of Figs . 8 and 10 .  In the embodiments of Figs. 8 and 10, instead of an insulating base film made of polyimide, a metal plate made of copper or 42% copper alloy with an electrically insulating layer on the surface thereof is used as a base film .However, such a base film of metal plate can also be used in the embodiments other than those of Figs .8 and 10.

In the embodiments as mentioned above , the lead frame can be made in accordance with a similar process for making a TAB tape , in which a copper foil is f irst formed on a base insulating f ilm and then a conductive pattern is formed by etching the copper foil . However , the lead frame can also be made in accordance with a process in which a lead pattern is f irst formed and then the lead pattern is supported by an insulating film . In any case , the lead frame thus made can be used to mount a semiconductor chip thereon and can be handled in the same manner as a conventional lead f rame , A semiconductor device product sealed with a resin can also be easily- handled , Therefore , in this specification , " lead frame " used for mounting thereon a semiconductor chip is also referred to as "TAB tape " , In the embodiments as mentioned above, the lead frame can be made in accordance with a similar process for making a TAB tape, in which a copper foil is f irst formed on a base insulating f ilm and then a conductive pattern is formed by etching the copper foil .However, the lead frame can also be made in accordance with a process in which a lead pattern is f irst formed and then the lead pattern is supported by an insulating film .In any case, the lead frame thus made can be used to mount a semiconductor chip thereon and can be handled in the same manner as a conventional lead f rame, A semiconductor device product sealed with a resin can also be easily- handled, There, in this specification, "lead frame" used for mounting thereon a semiconductor chip is also referred to as "TAB tape",

To increase the thickness of a part of the outer lead 20 , the outer leads can be plated partially with copper , in the embodiments as mentioned above . However , in practice , the following methods can be employed , in consideration of the bonding characteristic at the inner lead portions and the mounting characteristic at the outer lead portions . In any case , copper can be used as a base material to increase the thickness of the outer leads .  To increase the thickness of a part of the outer lead 20, the outer leads can be plated partially with copper, in the embodiments as mentioned above .However, in practice, the following methods can be employed, in consideration of the bonding characteristic at the inner lead portions and the mounting characteristic at the outer lead portions .In any case, copper can be used as a base material to increase the thickness of the outer leads.

( 1 ) he inner leads are plated with gold to form protective layers and the outer leads are plated with copper or solder to increase the thickness thereof . In this case , since it is relatively dif ficult to directly plate with gold, it is preferable that the entire lead surfaces including inner and outer leads are plated with nickel as an under layer, then all of the leads are plated with a gold , and then only the outer lead portions are subjected to plating to increase the thickness thereof - In this case , to increase the thickness , ' the outer leads may be plated with copper r plated with solder after plated with copper , or plated with solder in place of copper · Thus r the portions of the outer leads plated with copper or solder , which is exposed to the outside . (1) he inner leads are plated with gold to form protective layers and the outer leads are plated with copper or solder to increase the thickness that .In this case, since it is relatively dif ficult to directly plate with gold, it is preferred that the entire lead surfaces including inner and outer leads are plated with nickel as an under layer, then all of the leads are plated with a gold, and then only the outer lead portions are subjected to plating to increase the thickness agree-In this case, to increase the thickness, 'the outer leads may be plated with copper r plated with solder after plated with copper, or plated with solder in place of copper · Thus r the portions of the outer leads plated with copper or solder, which is exposed to the outside.

( 2 ) Both inner and outer leads are plated with palladium to form protective layers . In this case , in consideration of the bonding characteristic at the inner lead portions and the mounting characteristic at the outer lead portions r all the lead surfaces , including inner and outer leads , are plated with palladium . It is preferable that the copper foil is plated with nickel as an underlayer , then the outer lead portions are subjected to plating to increase the thickness thereof , and then the entire lead surface including inner and outer leads are plated with palladium - In this case , after the outer lead portions are plated with copper to increase the thickness thereof , solder may further be plated thereon . (2) Both inner and outer leads are plated with palladium to form protective layers .In this case, in consideration of the bonding characteristic at the inner lead portions and the mounting characteristic at the outer lead portions r all the lead surfaces, including inner and outer leads, are plated with palladium .It is preferred that the copper foil is plated with nickel as an underlayer, the the outer lead portions are subjected to plating to increase the thickness that, and then the entire lead surface including inner and outer leads are plated with palladium-In this case, after the outer lead portions are plated with copper to increase the thickness thereof, solder may further be plated thereon.

( 3 ) Both inner and outer leads are plated with tin to form a protective layer . In this case , since tin can be plated directly on the copper material without an underlayer , only the outer lead portions are first plated with a copper or solder to increase the thickness  (3) Both inner and outer leads are plated with tin to form a protective layer .In this case, since tin can be plated directly on the copper material without an underlayer, only the outer lead portions are first plated with a copper or solder to increase the thickness

thereof , and then all the lead surfaces including inner and outer leads are plated with a tin . In this case , the outer lead portions may be first plated with copper and then plated with solder to increase the thickness thereof and then the entire lead surface including inner and outer leads may be plated with tin . When, and then all the lead surfaces including inner and outer leads are plated with a tin .In this case, the outer lead portions may be first plated with copper and then plated with solder to increase the thickness thereof and then the entire lead surface including inner and outer leads may be plated with tin.

According to this method , since there is no  According to this method, since there is no

underlayer , the thickness of the inner leads can underlayer, the thickness of the inner leads can

advantageous ly be made as thin as possible and , advantageous ly be made as thin as possible and,

therefore , this method is particularly suitable for making a TAB tape having fine patterns , therefore, this method is particularly suitable for making a TAB tape having fine patterns,

In the above-mentioned embodiments , the thickness of the plated layer can advantageous ly be selected in such a manner that the thickness of the plated gold is 0 , 3 to 5μπι, the thickness of the plated nickel is 1 to 20μπι/ the thickness of the plated palladium is 0 . 1 to 0 . 5μπι, and the thickness of the plated tin is about 0 . 5μιη . In the above-mentioned embodiments, the thickness of the plated layer can advantageous ly be selected in such a manner that the thickness of the plated gold is 0, 3 to 5 μπι, the thickness of the plated nickel is 1 to 20 μπι / the thickness of the plated palladium is 0 .1 to 0.5 μπι, and the thickness of the plated tin is about 0 .5 μιη.

The thickness of the plated layer for increasing the thickness of the outer leads may be 50 to 70μπι . Since the base copper material has a thickness of about several tens of ιτι^ the entire thickness of the outer lead including the plated underlayer or the like may thus be about ΙΟΟμπι .  The thickness of the plated layer for increasing the thickness of the outer leads may be 50 to 70 μπι .Since the base copper material has a thickness of about several tens of ιτι ^ the entire thickness of the outer lead including the plated underlayer or the like may thus be about ΙΟΟμπι.

Although in the above-mentioned embodiments , the outer leads are subjected to plating to increase the thickness thereof , the thickness of the outer leads 20 may be increased by any other method , such as sputtering , vapor deposition , or the like method .  Although in the above-mentioned embodiments, the outer leads are subjected to plating to increase the thickness that, the thickness of the outer leads 20 may be increased by any other method, such as sputtering, vapor deposition, or the like method.

It should be understood by those skilled in the art that the foregoing description relates to only a It should be understood by those skilled in the art that the associated description relates to only a

preferred embodiment of the disclosed invention , and that various changes and modifications may be made to the invention without departing from the spirit and scope thereof · preferred embodiment of the disclosed invention, and that various changes and modifications may be made to the invention without departing from the spirit and scope thereof

INDUSTRIAL APPLICABILITY  INDUSTRIAL APPLICABILITY

As mentioned above r according to the present As mentioned above r according to the present

invention , a useful and improved lead frame and invention, a useful and improved lead frame and

semiconductor devices using the same can thus be semiconductor devices using the same can thus be

provided . provided.

Claims

CLAIMS 1 . A lead frame adapted to be used for a  1.A lead frame adapted to be used for a semiconductor device comprising : semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily forming a fine pattern of said inner leads； and  a plurality of inner leads made of a thin conductive material for easily forming a fine pattern of said inner leads; and a plurality of outer leads integrally formed with said respective inner leads , said outer leads being coated with metal layers to increase a thickness thereof , so that a desired strength of said outer leads is obtained .  a plurality of outer leads formed with said respective inner leads, said outer leads being coated with metal layers to increase a thickness there, so that a desired strength of said outer leads is obtained. 2 . A lead frame as set forth in claim 1 , wherein said outer leads are plated with a metal which is the same material as said inner and outer leads .  2.A lead frame as set forth in claim 1, ,, said said outer leads are plated with a metal which is the same material as said inner and outer leads. 3 . A lead frame as set forth in claim 2 , wherein all the surfaces of said inner leads and said outer leads are plated with gold , silver , palladium, tin or the like , as a protective metal layer .  3.A lead frame as set forth in claim 2,, combined all the surfaces of said inner leads and said outer leads are plated with gold, silver, palladium, tin or the like, as a protective metal layer. 4 , A lead frame adapted to be used for a  4, A lead frame adapted to be used for a semiconductor device comprising : semiconductor device comprising: an insulating base film;  an insulating base film; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads； and said inner leads being relatively thin , but said outer leads being coated with metal layers to increase the thickness thereof , so that a desired  a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads related formed with said respective inner leads; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness there, so that a desired strength of said outer leads is obtained . strength of said outer leads is obtained. 5 . A lead frame as set forth in claim 4 , wherein said outer leads are plated with a metal which is the same material as said inner and outer leads .  5.A lead frame as set forth in claim 4, ,, said outer leads are plated with a metal which is the same material as said inner and outer leads. 6 . A lead frame as set forth in claim 5 , wherein all the surfaces of said inner leads and said outer leads are plated with gold , silver, palladium, tin or the like , as a protective metal layer .  6.A lead frame as set forth in claim 5,,, all the surfaces of said inner leads and said outer leads are plated with gold, silver, palladium, tin or the like, as a protective metal layer. 7 . A lead frame as set forth in claim 4 , wherein said insulating base film has a device hole at a central position thereof and window holes located apart from said central device hole , each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole . 7 .A lead frame as set forth in claim 4,. said insulating base film has a device hole at a central position there and window holes located apart from said central device hole, each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole . 8 . A lead frame as set forth in claim 4 , wherein a die-pad is formed as a part of said conductive pattern formed on said insulating base film at a central position thereof , and said insulating base film has window holes located apart from said die-pad , each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole .  8.A lead frame as set forth in claim 4, ,, a die-pad is formed as a part of said conductive pattern formed on said insulating base film at a central position there, and said insulating base film has window holes located apart from said. die-pad, each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole. 9 . A lead frame as set forth in claim 4 , wherein said outer leads are continuously connected to each other by means of a tie bar which is a part of said conductive pattern formed on said insulating base film.  9.A lead frame as set forth in claim 4, ,, said outer leads are continuously connected to each other by means of a tie bar which is a part of said conductive pattern formed on said insulating base film. 10 . A process for making a lead frame adapted to be used for a semiconductor device which comprises the steps of :  10.A process for making a lead frame adapted to be used for a semiconductor device which comprises the steps of: forming a conductive layer on a insulating base film;  forming a conductive layer on a insulating base film; etching said conductive layer to form a conductive pattern including a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads； and  etching said conductive layer to form a conductive pattern including a plurality of inner leads and a plurality of outer leads formed with said respective inner leads; and coating said outer leads with metal layers to increase the thickness of said outer leads r so that a desired strength of said outer leads is obtained . coating said outer leads with metal layers to increase the thickness of said outer leads r so that a desired strength of said outer leads is obtained. 11 . A process as set forth in claim 10 , wherein said coating step comprises a step of plating said outer leads with a metal which is the same material as said inner and outer leads to increase the thickness of said outer leads .  11.A process as set forth in claim 10, ,, said coating step comprises a step of plating said outer leads with a metal which is the same material as said inner and outer leads to increase the thickness of said outer leads. 12 . A process as set forth in claim 11 , wherein said coating step comprises a step of plating all the surfaces at said inner leads and said outer leads with gold , silver , palladium, tin or the like , as a protective metal layer . 12.A process as set forth in claim 11, ,, said coating step includes a step of plating all the surfaces at said inner leads and said outer leads with gold, silver, palladium, tin or the like, as a protective metal layer. 13 . A process for making a lead frame adapted to be used for a semiconductor device which comprises the steps of :  13.A process for making a lead frame adapted to be used for a semiconductor device which comprises the steps of: forming a conductive layer on an  forming a conductive layer on an insulating base film having a device hole at a central position thereof and window holes located apart from said central device hole ; insulating base film having a device hole at a central position there and window holes located apart from said central device hole; etching said conductive layer to form a conductive pattern including a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole ; and  etching said conductive layer to form a conductive pattern including a plurality of inner leads and a plurality of outer leads reform formed with said respective inner leads, so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole; and coating said outer leads with metal layers to increase the thickness thereof , so that a desired strength of said outer leads is obtained .  coating said outer leads with metal layers to increase the thickness there, so that a desired strength of said outer leads is obtained. 14 . A process for making a lead frame adapted to be used for a semiconductor device which comprises the steps of :  14.A process for making a lead frame adapted to be used for a semiconductor device which comprises the steps of: forming a conductive layer on an  forming a conductive layer on an insulating base f ilm having window holes located apart from a central position of said base film; insulating base f ilm having window holes located apart from a central position of said base film; etching said conductive layer to form a conductive pattern including a die-pad located at a central position of said insulating base film, a  etching said conductive layer to form a conductive pattern including a die-pad located at a central position of said insulating base film, a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole ; and plurality of inner leads and a plurality of outer leads derived formed with said respective inner leads, so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole; and coating said outer leads with metal layers to increase the thickness thereof , so that a desired strength of said outer leads is obtained . coating said outer leads with metal layers to increase the thickness there, so that a desired strength of said outer leads is obtained. 15 . A semiconductor device comprising : 15.A semiconductor device comprising: ( a ) a lead frame adapted to be used for a semiconductor device comprising :  (a) a lead frame adapted to be used for a semiconductor device comprising: a plurality of inner leads made of a thin conductive material for easily forming a fine pattern of said inner leads ; and  a plurality of inner leads made of a thin conductive material for easily forming a fine pattern of said inner leads; and a plurality of outer leads integrally formed with said respective inner leads , said outer leads being coated with metal layers to increase the thickness thereof , so that a desired strength of said outer leads is obtained;  a plurality of outer leads formed with said respective inner leads, said outer leads being coated with metal layers to increase the thickness there, so that a desired strength of said outer leads is obtained; ( b ) a semiconductor chip electrically connected to said inner leads； and  (b) a semiconductor chip electrically connected to said inner leads; and ( c ) a resin for hermetically sealing said semiconductor chip and a part of said lead frame  (c) a resin for hermetically sealing said semiconductor chip and a part of said lead frame including said inner leads · including said inner leads 16 . A semiconductor device comprising :  16.A semiconductor device comprising: ( a ) a lead frame comprising：  (a) a lead frame comprising: an insulating base film having a device hole at a central position thereof and window holes located apart from said device hole ;  an insulating base film having a device hole at a central position there and window holes located apart from said device hole; a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole ; and said inner leads being relatively thin , but said outer leads being coated with metal layers to increase the thickness thereof , so that a desired  a conductive pattern formed on said insulating base film, said conductive pattern including a plurality of inner leads and a plurality of outer leads related formed with said respective inner leads, so that each said inner lead extends inward into said central device hole and each said outer lead extends outward from said inner lead over said window hole; and said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness there, so that a desired strength of said outer leads is obtained ; strength of said outer leads is obtained; ( b ) a semiconductor chip mounted on and electrically connected to said inner leads within said central opening ; and  (b) a semiconductor chip mounted on and electrically connected to said inner leads within said central opening; and ( c ) a resin for hermetically sealing said semiconductor chip and a part of said lead frame including said inner leads . (c) a resin for hermetically sealing said semiconductor chip and a part of said lead frame including said inner leads. 17 . A semiconductor device comprising :  17.A semiconductor device comprising: ( a ) a lead frame comprising :  (a) a lead frame comprising: an insulating base film having window holes located apart from a central position of said base film;  an insulating base film having window holes located apart from a central position of said base film; a conductive pattern formed on said insulating base film, said conductive pattern including a Iplurality of inner leads and a plurality of outer leads integrally formed with said respective inner leads , so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole ; and  a conductive pattern formed on said insulating base film, said conductive pattern including a Iplurality of inner leads and a plurality of outer leads sole formed with said respective inner leads, so that each said inner lead extends toward said die-pad and each said outer lead extends outward from said inner lead over said window hole; and said inner leads being relatively thin , but said outer leads being coated with metal layers to increase the thickness thereof , so that a desired  said inner leads being relatively thin, but said outer leads being coated with metal layers to increase the thickness there, so that a desired strength of said outer leads is obtained; strength of said outer leads is obtained; (b ) a semiconductor chip mounted on said die- pad ;  (b) a semiconductor chip mounted on said die- pad; ( c ) bonding wires for electrically connecting said semiconductor chip to said inner leads ; and  (c) bonding wires for electrically connecting said semiconductor chip to said inner leads; and ( d ) a resin for hermetically sealing said semiconductor chip and a part of said lead frame  (d) a resin for hermetically sealing said semiconductor chip and a part of said lead frame including said inner leads . including said inner leads.
EP93924830A 1992-11-17 1993-11-16 Lead frame and semiconductor device using same Ceased EP0621982A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP332531/92 1992-11-17
JP33253192 1992-11-17
JP63738/93 1993-03-23
JP6373893 1993-03-23
PCT/JP1993/001677 WO1994011902A1 (en) 1992-11-17 1993-11-16 Lead frame and semiconductor device using same

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US6184575B1 (en) 1994-08-26 2001-02-06 National Semiconductor Corporation Ultra-thin composite package for integrated circuits
DE10237084A1 (en) 2002-08-05 2004-02-19 Osram Opto Semiconductors Gmbh Electrically conductive frame with a semiconductor light diode, to illuminate a mobile telephone keypad, has a layered structure with the electrical connections and an encapsulated diode chip in very small dimensions
CN100533723C (en) * 2002-08-05 2009-08-26 奥斯兰姆奥普托半导体有限责任公司 Manufacturing method of electric lead frame, manufacturing method of surface mounted semiconductor device and lead frame tape
JP4688647B2 (en) * 2005-11-21 2011-05-25 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP5971531B2 (en) * 2014-04-22 2016-08-17 大日本印刷株式会社 Resin-sealed semiconductor device and manufacturing method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT315947B (en) * 1971-03-26 1974-06-25 Interelectric Ag Method for producing a leadframe for integrated circuits
JPH0612796B2 (en) * 1984-06-04 1994-02-16 株式会社日立製作所 Semiconductor device
JPH06101492B2 (en) * 1986-02-24 1994-12-12 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JPS63239829A (en) * 1987-03-27 1988-10-05 Hitachi Ltd electronic equipment
JPH02250364A (en) * 1989-03-23 1990-10-08 Toppan Printing Co Ltd Lead frame and its manufacturing method
JPH04102341A (en) * 1990-08-22 1992-04-03 Shinko Electric Ind Co Ltd Manufacture of tab tape

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9411902A1 *

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JPH07506935A (en) 1995-07-27

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