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EP0651311A2 - Selbsterregende Konstantstromquelle - Google Patents

Selbsterregende Konstantstromquelle Download PDF

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Publication number
EP0651311A2
EP0651311A2 EP19940116889 EP94116889A EP0651311A2 EP 0651311 A2 EP0651311 A2 EP 0651311A2 EP 19940116889 EP19940116889 EP 19940116889 EP 94116889 A EP94116889 A EP 94116889A EP 0651311 A2 EP0651311 A2 EP 0651311A2
Authority
EP
European Patent Office
Prior art keywords
node
current mirror
channel mos
voltage line
low voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19940116889
Other languages
English (en)
French (fr)
Inventor
Hidenao Sajtoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0651311A2 publication Critical patent/EP0651311A2/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to a constant current circuit, and more particularly to a circuitry for starting in self-excitation a constant current circuit involved in a CMOS integrated circuit.
  • the conventional constant current circuit includes first and second current mirror circuits M1 and M2 and a resistance R1, that are provided between high and low voltage lines that supply high and low voltages V DD and V SS respectively.
  • the first current mirror circuit M1 includes a first n-channel MOS transistor T1 and a second n-channel MOS transistor T2, while the second current mirror circuit M2 includes a first p-channel MOS transistor T3 and a second p-channel MOS transistor T4.
  • the first n-channel MOS transistor T1 has a source electrically connected to a resistance R1 that is connected to the low voltage line V SS , a drain electrically connected to a first node N1, a gate connected to a gate of the second n-channel MOS transistor T2 and a substrate electrically connected to the low voltage line.
  • the second n-channel MOS transistor has the gate connected to the gate of the first n-channel MOS transistor, a drain electrically connected to the gate through a second node N2, a source electrically connected to the low voltage line and a substrate electrically connected to the source.
  • the second n-channel MOS transistor including the gate-drain connection performs as a diode.
  • the second current mirror circuit M2 includes a first p-channel MOS transistor T3 and a second p-channel MOS transistor T4.
  • the first p-channel MOS transistor T3 has a source electrically connected to the high voltage line, a drain electrically connected to the first node N1 that is connected to the drain of the first n-channel MOS transistor T1, a gate electrically connected both to a gate of the second p-channel MOS transistor T4 and to the drain thereof and a substrate connected to the source thereof.
  • the first p-channel MOS transistor T3 having the gate drain connection performs as a diode.
  • the second p-channel MOS transistor T4 has a source connected to the high voltage line, a drain connected to the second node N2 that is connected to the drain of the second n-channel MOS transistor T2, the gate connected to the first p-channel MOS transistor T3 and a substrate connected to the source thereof.
  • the conventional constant current circuit further includes a third p-channel MOS transistor T11 and third and fourth n-channel MOS transistors T10 and T12.
  • the third p-channel MOS transistor T11 has a source connected to the high voltage line, a drain connected to a drain of the third n-channel MOS transistor T10, a gate connected to the first node N1 and a substrate connected to the source thereof.
  • the third n-channel MOS transistor T10 has a source connected to the low voltage line, the drain connected to the drain of the third p-channel MOS transistor T11, a gate connected to the drain thereof and a substrate connected to the source thereof.
  • the fourth n-channel MOS transistor T12 has a source connected to the low voltage line, a drain connected to the first node N1, a gate receiving a start or reset signal and a substrate connected to the low voltage line and the source of the third n-channel MOS transistor T10. Then, the source and substrate of the third n-channel MOS transistor T10 as well as the substrate of the fourth n-channel MOS transistor T12 are connected to the low voltage line.
  • the third p-channel MOS transistor T11 is provided to form a third current mirror circuit in cooperation with the first p-channel MOS transistor T3.
  • the first, second and third current mirror circuits have first, second and third current gain values respectively.
  • the first n-channel MOS transistor T1 has a third drain current I3.
  • the second n-channel MOS transistor T2 and the second p-channel MOS transistor T4 have a second drain current I2.
  • the first p-channel MOS transistor T3 has a first drain current.
  • the first current gain value of the first current mirror circuit M1 defines a ratio of the second drain current I2 to the third drain current value I3.
  • the first current gain value of the first current mirror circuit M1 depends upon a resistance value of the resistance R1.
  • the second current gain value of the second current mirror circuit M1 defines a ratio of the second drain current I2 to the first drain current value I1.
  • the third drain current corresponds to the sum of the first drain current and a current flowing through the fourth n-channel MOS transistor T12.
  • the third current mirror circuit comprising the first p-channel MOS transistor T3 and the third p-channel MOS transistor T11 performs to induce an output current I0 from the high voltage line into the source of the third p-channel MOS transistor T11.
  • the gate of the fourth n-channel MOS transistor receives a reset signal comprising a high voltage signal thereby the fourth n-channel MOS transistor turns ON.
  • the low voltage V SS is supplied from the low voltage line through the ON-state fourth n-channel MOS transistor T12 to the gates of the first to third p-channel MOS transistors T3, T4 and T11 thereby the first to third p-channel MOS transistors T3, T4 and T11 turn ON.
  • the high voltage V DD is supplied from the high voltage line through the second p-channel MOS transistor T4 into the second node N2.
  • the high voltage V DD of the second node N2 is then supplied to the gates of the first and second n-channel MOS transistors thereby the first and second n-channel MOS transistors T1 and T2 turn ON. Further, the high voltage V SS is supplied from the high voltage line through the third p-channel MOS transistor T11 to the gate of the third n-channel MOS transistor T10 thereby the third n-channel MOS transistor T10 turns ON. Namely, applying the high level signal to the gate of the fourth n-channel MOS transistor T12 results in turning ON of all the transistors.
  • the operations of the constant current circuit is stabilized at an operational point where the product of the first and second current gains is 1. In the stable point, the output current is fetched through the third current mirror circuit including the third p-channel MOS transistor T11.
  • the above described convention constant current circuit has disadvantages as described below.
  • the conventional circuit requires a further external circuit for generating a reset signal as an external signal to be applied to the gate of the fourth n-channel MOS transistor T10.
  • the external circuit is required to have a detector for detecting applications of the high voltage and a trigger circuit for outputting the external signal. In the above circuit, is is possible that variations of the power source voltage, particularly in a rapid drop of the high voltage appears.
  • the variation of the power source voltage such as the rapid drop of the high voltage results in that a closed loop circuit comprising the first and second current mirror circuits M1 and M2 may be made stable without any operational point where all of the transistors involved in the first and second current mirror circuits MI and M2 are in Off state and then the constant current circuit exhibits no output current.
  • FIG. 3 illustrates a circuit configuration of the constant current circuit with the self-excitation starting circuit.
  • the circuit configuration of the constant current circuit with the self-excitation starting circuit has the same structure of the conventional circuit as illustrated in FIG. 1 except for providing two of extra n-channel and p-channel MOS transistors T13 and T14 both between the first node N1 and the high voltage line and between the low voltage line and the second node N2.
  • the another conventional constant current circuit includes the first and second current mirror circuits M1 and M2 and a resistance R1, that are provided between the high and low voltage lines that supply the high and low voltages V DD and V SS respectively.
  • the first current mirror circuit M1 includes the first n-channel MOS transistor T1 and the second n-channel MOS transistor T2, while the second current mirror circuit M2 includes the first p-channel MOS transistor T3 and the second p-channel MOS transistor T4.
  • the first n-channel MOS transistor T1 has the source electrically connected to the resistance R1 that is connected to the low voltage line V SS , a drain electrically connected to the first node N1, a gate connected to a gate of the second n-channel MOS transistor T2 and a substrate electrically connected to the low voltage line.
  • the second n-channel MOS transistor has the gate connected to the gate of the first n-channel MOS transistor, a drain electrically connected to the gate through the second node N2, the source electrically connected to the low voltage line and a substrate electrically connected to the source.
  • the second n-channel MOS transistor including the gate-drain connection performs as a diode.
  • the second current mirror circuit M2 includes the first p-channel MOS transistor T3 and the second p-channel MOS transistor T4.
  • the first p-channel MOS transistor T3 has the source electrically connected to the high voltage line, a drain electrically connected to the first node N1 that is connected to the drain of the first n-channel MOS transistor T1, a gate electrically connected both to a gate of the second p-channel MOS transistor T4 and to the drain thereof and a substrate connected to the source thereof.
  • the first p-channel MOS transistor T3 having the gate drain connection performs as a diode.
  • the second p-channel MOS transistor T4 has a source connected to the high voltage line, a drain connected to the second node N2 that is connected to the drain of the second n-channel MOS transistor T2, the gate connected to the first p-channel MOS transistor T3 and a substrate connected to the source thereof.
  • the conventional constant current circuit further includes the third p-channel MOS transistor T11 and the third and fourth n-channel MOS transistors T10 and T12.
  • the third p-channel MOS transistor T11 has a source connected to the high voltage line, a drain connected to a drain of the third n-channel MOS transistor T10, a gate connected to the first node N1 and a substrate connected to the source thereof.
  • the third n-channel MOS transistor T10 has a source connected to the low voltage line, the drain connected to the drain of the third p-channel MOS transistor T11, a gate connected to the drain thereof and a substrate connected to the source thereof.
  • the fourth n-channel MOS transistor T12 has a source connected to the low voltage line, a drain connected to the first node N1, a gate receiving a start or reset signal and a substrate connected to the low voltage line and the source of the third n-channel MOS transistor T10. Then, the source and substrate of the third n-channel MOS transistor T10 as well as the substrate of the fourth n-channel MOS transistor T12 are connected to the low voltage line.
  • the third p-channel MOS transistor T11 is provided to form a third current mirror circuit in cooperation with the first p-channel MOS transistor T3.
  • the first, second and third current mirror circuits have first, second and third current gain values respectively.
  • the first n-channel MOS transistor T1 has the third drain current I3.
  • the second n-channel MOS transistor T2 and the second p-channel MOS transistor T4 have the second drain current I2.
  • the first p-channel MOS transistor T3 has the first drain current.
  • the first current gain value of the first current mirror circuit M1 defines a ratio of the second drain current I2 to the third drain current value I3.
  • the first current gain value of the first current mirror circuit M1 depends upon a resistance value of the resistance R1.
  • the second current gain value of the second current mirror circuit M1 defines a ratio of the second drain current I2 to the first drain current value I1.
  • the third drain current corresponds to the sum of the first drain current and a current flowing through the fourth n-channel MOS transistor T12.
  • the third current mirror circuit comprising the first p-channel MOS transistor T3 and the third p-channel MOS transistor T11 performs to induce an output current I0 from the high voltage line into the source of the third p-channel MOS transistor T11.
  • the another conventional constant current circuit further includes the fifth n-channel MOS transistor T13 and the fourth p-channel MOS transistor T14.
  • the fifth n-channel MOS transistor T13 is provided between the low voltage line and the second node N2.
  • the fifth n-channel MOS transistor T13 has a gate electrically connected to the low voltage line, a source connected to the low voltage line, a drain connected to the second node N2 and a substrate connected to the low voltage line.
  • the fourth p-channel MOS transistor T14 is provided between the high voltage line and the first node N1.
  • the fourth p-channel MOS transistor T14 has a gate electrically connected to the high voltage line, a source connected to the high voltage line, a drain connected to the first node N2 and a substrate connected to the high voltage line.
  • the gate of the fifth n-channel MOS transistor T13 is directly connected to the low voltage line so that the low level signal is always applied to the gate of the fifth n-channel MOS transistor T13 thereby the fifth n-channel MOS transistor T13 always remains in the off state.
  • the gate of the fourth p-channel MOS transistor T14 is directly connected to the high voltage line so that the high level signal is always applied to the gate of the fourth p-channel MOS transistor T14 thereby the fourth p-channel MOS transistor T14 always remains in the off state.
  • the fifth n-channel and fourth p-channel MOS transistors T13 and T14 may supply leakage currents in the off-state or off-leak current to the second and first nodes N2 and N1 respectively for realizing the self-excitation. Namely, the off-leak current is used as a self-excitation current.
  • the above self-excitation system using the off-leakage current is however engaged with the following problems.
  • the off-leak current is kept to flow during the stationary state of the constant current circuit. This results in an increase of power consumptions. Further, the off-leak current causes a problem with unnecessary heat generation that makes it difficult to layout the circuit configuration in view of the circuit design. It would therefore be required to suppress any current flow for the self-exciting except for the time of starting the constant current circuit.
  • the invention provides a circuitry comprising first and second current mirror circuits and a voltage control device.
  • the first current mirror circuit is connected to a high voltage line that supplies a predetermined high voltage.
  • the first current mirror circuit has an input side through which a first current flows and an output side through which a second current flows.
  • the second current mirror circuit is connected to a low voltage line that supplies a predetermined low voltage.
  • the second current mirror circuit has an output side being connected through a first node to the input side of the first current mirror circuit and an input side being connected through a second node to the output side of the first current mirror circuit in which the second current flows through the input side of the second current mirror circuit as well as a third current flows through the output side of the second current mirror circuit.
  • the voltage control device is electrically connected between the first node and the low voltage line for controlling, only in starting the circuitry, a potential of the first node at a predetermined stationary potential value where the first and second current mirror circuits are in a stationary and operational state.
  • the voltage control device may comprise a switching circuit being electrically connected between the first node and the low voltage line.
  • the switching circuit has a threshold voltage that is just higher than the predetermined stationary potential value so that just when the potential of the first node comes beyond the predetermined stationary potential value then the switching circuit turns ON to thereby render the first node electrically conductive to the low voltage line for drop of the potential of the first node down to the predetermined stationary potential value.
  • the switching circuit comprises a series connection of a plurality of field effect transistors between the first node and the low voltage line in which a sum of threshold voltages of the individual plural field effect transistors corresponds to the threshold voltage of the switching circuit.
  • Each of the plural field effect transistors involved in the switching circuit has a substrate connected to the low voltage line and a gate connected at the first node side to an adjacent one of the field effect transistors to form a diode connection between the first node and the low voltage line.
  • FIG. 1 is a circuit diagram illustrative of the conventional constant current circuit.
  • FIG. 2 is a circuit diagram illustrative of the another conventional constant circuit.
  • FIG. 3 is a circuit diagram illustrative of a novel constant current circuit of a preferred embodiment according to the present invention. A first embodiment of the present invention will be described with reference to FIG. 3 in which a novel constant current circuitry is provided.
  • the novel constant current circuit according to the present invention includes first and second current mirror circuits M1 and M2 and a resistance R1, that are provided between high and low voltage lines that supply high and low voltages V DD and V SS respectively as well as an improved self-exciting circuit comprising a switching circuit for realizing a self-excitation in which a current flow for self-excitation appears only in starting the constant current circuit.
  • the improved self-exciting circuit as the swicthing circuit is provided between an output side of the second current mirror circuit and any one of the high and low voltage lines.
  • the first current mirror circuit M1 includes a first n-channel MOS transistor T1 and a second n-channel MOS transistor T2, while the second current mirror circuit M2 includes a first p-channel MOS transistor T3 and a second p-channel MOS transistor 74.
  • the first n-channel MOS transistor T1 has a source electrically connected to a resistance R1 that is connected to the low voltage line V SS , a drain electrically connected to a first node N1, a gate connected to a gate of the second n-channel MOS transistor T2 and a substrate electrically connected to the low voltage line.
  • the second n-channel MOS transistor has the gate connected to the gate of the first n-channel MOS transistor, a drain electrically connected to the gate through a second node N2, a source electrically connected to the low voltage line and a substrate electrically connected to the source.
  • the second n-channel MOS transistor including the gate-drain connection performs as a diode.
  • the second current mirror circuit M2 includes a first p-channel MOS transistor T3 and a second p-channel MOS transistor T4.
  • the first p-channel MOS transistor T3 has a source electrically connected to the high voltage line, a drain electrically connected to the first node N1 that is connected to the drain of the first n-channel MOS transistor T1, a gate electrically connected both to a gate of the second p-channel MOS transistor T4 and to the drain thereof and a substrate connected to the source thereof.
  • the first p-channel MOS transistor T3 having the gate drain connection performs as a diode.
  • the second p-channel MOS transistor T4 has a source connected to the high voltage line, a drain connected to the second node N2 that is connected to the drain of the second n-channel MOS transistor T2, the gate connected to the first p-channel MOS transistor T3 and a substrate connected to the source thereof.
  • the novel constant current circuit further includes a third p-channel MOS transistor T11 and a third n-channel MOS transistor T10.
  • the third p-channel MOS transistor T11 has a source connected to the high voltage line, a drain connected to a drain of the third n-channel MOS transistor T10, a gate connected to the first node N1 and a substrate connected to the source thereof.
  • the third n-channel MOS transistor T10 has a source connected to the low voltage line, the drain connected to the drain of the third p-channel MOS transistor T11, a gate connected to the drain thereof and a substrate connected to the low voltage line.
  • the novel constant current circuit further includes a switching circuit S1 for self-excitation of the constant current circuit.
  • the switching circuit S1 is provided between the node N1 and the low voltage line.
  • the switching circuit comprises series connections of five n-channel MOS transistors T5 to T9 between the low voltage line and the first node N1.
  • the n-channel MOS transistor T5 has a source, a gate connected to the first node N1, a drain connected to the first node N1 and a substrate connected to the low voltage line.
  • the n-channel MOS transistor T6 has a source, a gate connected to the source of the n-channel MOS transistor T5, a drain connected to the source of the n-channel MOS transistor T5 and a substrate connected to the low voltage line.
  • the n-channel MOS transistor T7 has a source, a gate connected to the source of the n-channel MOS transistor T6, a drain connected to the source of the n-channel MOS transistor T6 and a substrate connected to the low voltage line.
  • the n-channel MOS transistor T8 has a source, a gate connected to the source of the n-channel MOS transistor T7, a drain connected to the source of the n-channel MOS transistor T7 and a substrate connected to the low voltage line.
  • the n-channel MOS transistor T9 has a source connected to the low voltage line, a gate connected to the source of the n-channel MOS transistor T8, a drain connected to the source of the n-channel MOS transistor T8 and a substrate connected to the low voltage line.
  • the switching circuit comprising the series connections of the n-channel MOS transistors T5 to T9 has a predetermined threshold voltage that almost corresponds to the sum of threshold voltages of the individual n-channel MOS transistors T5 to T9.
  • the third p-channel MOS transistor T11 is provided to form a third current mirror circuit in cooperation with the first p-channel MOS transistor T3.
  • the first, second and third current mirror circuits have first, second and third current gain values respectively.
  • the first n-channel MOS transistor T1 has a third drain current I3.
  • the second n-channel MOS transistor T2 and the second p-channel MOS transistor T4 have a second drain current I2.
  • the first p-channel MOS transistor T3 has a first drain current.
  • the first current gain value of the first current mirror circuit M1 defines a ratio of the second drain current I2 to the third drain current value I3.
  • the first current gain value of the first current mirror circuit M1 depends upon a resistance value of the resistance R1.
  • the second current gain value of the second current mirror circuit M1 defines a ratio of the second drain current I2 to the first drain current value I1.
  • the third drain current I3 corresponds to the sum of the first drain current and a current flowing through the fourth n-channel MOS transistor T12.
  • the third current mirror circuit comprising the first p-channel MOS transistor T3 and the third p-channel MOS transistor T11 performs to induce an output current I0 from the high voltage line into the source of the third p-channel MOS transistor T11.
  • the high and low voltage lines may have voltages of 5V and 0V respectively.
  • the constant current circuit may be stabilized at the operational point where the product of the first and second current gain values of the first and second current mirror circuits MI and M2 comes into 1.
  • the first drain current value I1 is defined by both length and width of the individual gate of the first and second n-channel and p-channel MOS transistors T1, T2, T3 and T4 as well as a resistance value of the resistance R1.
  • a potential V N1 of the first node N1 is varied in the range of from 0V to 5V by variation of the first drain current I1.
  • Power ON or rapid drop of the power source voltage may cause that a potential V N2 of the second node N2 comes into a lower voltage than a threshold voltage V thT2 of the second n-channel MOS transistor T2 as well as the potential V N1 of the first node N1 comes into a lower voltage than a threshold voltage V thT3 of the first p-channel MOS transistor T3.
  • all the first and second n-channel and p-channel MOS transistors T1, T2, T3 and T4 come into the cut-off state so that none of the first and second drain current flows.
  • This cut-off state causes a voltage increase of first node N1 toward the high voltage V DD of the high voltage line.
  • the switching circuit S1 comes into ON state thereby the first node N1 is made into electrically conductive to the low voltage line. This results in a potential drop of the first node N1.
  • the potential drop of the first node N1 causes a current flow of the first drain current I1 so that the first and second current mirror circuits M1 and M2 are stabilized at the operational point where product of the first and second current gain values of the first and second mirror circuits M1 and M2 comes into 1.
  • the n-channel MOS transistors T5, T6, T7, T8 and T9 connected in series between the low voltage line and the first node N1 remain in the cut-off state.
  • the threshold voltage of the switching circuit S1 is required to be higher than a potential value of the first node N1 under the stable operational point of the constant current circuit but lower than the high voltage V DD of the high voltage line. Consequently, under the stationary operational state of the constant current circuit, the switching circuit is kept in the off state, while in starting the constant current circuit the switching circuit comes into the ON state to thereby establish the self-exciting circuit with the negative feedback function.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
EP19940116889 1993-10-27 1994-10-26 Selbsterregende Konstantstromquelle Withdrawn EP0651311A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP292633/93 1993-10-27
JP29263393A JPH07121255A (ja) 1993-10-27 1993-10-27 定電流源回路

Publications (1)

Publication Number Publication Date
EP0651311A2 true EP0651311A2 (de) 1995-05-03

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Family Applications (1)

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EP19940116889 Withdrawn EP0651311A2 (de) 1993-10-27 1994-10-26 Selbsterregende Konstantstromquelle

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EP (1) EP0651311A2 (de)
JP (1) JPH07121255A (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999050731A1 (en) * 1998-03-30 1999-10-07 Astrazeneca Ab Electrical device
EP1898293A1 (de) * 2006-08-28 2008-03-12 NEC Electronics Corporation Konstantstromschaltung
US8933682B2 (en) 2009-08-14 2015-01-13 Spansion Llc Bandgap voltage reference circuit

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3399433B2 (ja) 2000-02-08 2003-04-21 松下電器産業株式会社 基準電圧発生回路
FR2860307B1 (fr) * 2003-09-26 2005-11-18 Atmel Grenoble Sa Circuit integre avec fonction de demarrage automatique
KR100685090B1 (ko) * 2006-01-05 2007-02-22 주식회사 케이이씨 정전류 구동 회로
JP4835237B2 (ja) * 2006-04-05 2011-12-14 セイコーエプソン株式会社 電流源回路、およびこれを含むコンパレータ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59133618A (ja) * 1983-01-21 1984-08-01 Hitachi Ltd バイアス発生回路
JPS616717A (ja) * 1984-06-21 1986-01-13 Matsushita Electric Ind Co Ltd 基準出力回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999050731A1 (en) * 1998-03-30 1999-10-07 Astrazeneca Ab Electrical device
EP1898293A1 (de) * 2006-08-28 2008-03-12 NEC Electronics Corporation Konstantstromschaltung
US7609106B2 (en) 2006-08-28 2009-10-27 Nec Electronics Corporation Constant current circuit
US8933682B2 (en) 2009-08-14 2015-01-13 Spansion Llc Bandgap voltage reference circuit

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Publication number Publication date
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