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EP0492838B1 - Appareil pour augmenter le performance d'un tampon de traduction d'adresses - Google Patents

Appareil pour augmenter le performance d'un tampon de traduction d'adresses Download PDF

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Publication number
EP0492838B1
EP0492838B1 EP91311242A EP91311242A EP0492838B1 EP 0492838 B1 EP0492838 B1 EP 0492838B1 EP 91311242 A EP91311242 A EP 91311242A EP 91311242 A EP91311242 A EP 91311242A EP 0492838 B1 EP0492838 B1 EP 0492838B1
Authority
EP
European Patent Office
Prior art keywords
address
virtual
lookaside buffer
translation lookaside
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91311242A
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German (de)
English (en)
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EP0492838A3 (en
EP0492838A2 (fr
Inventor
Robert Becker
Peter Mehring
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
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Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of EP0492838A2 publication Critical patent/EP0492838A2/fr
Publication of EP0492838A3 publication Critical patent/EP0492838A3/en
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Publication of EP0492838B1 publication Critical patent/EP0492838B1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Definitions

  • This invention relates to computer memory management units and, more particularly, to apparatus for increasing the number of hits which occur in a translation lookaside buffer portion of a memory management unit.
  • a virtual memory system is one which allows addressing of very large amounts of memory as though all of that memory were the main memory of the computer system even though actual main memory may consist of some substantially lesser amount of storage space.
  • main memory may consist of one megabyte of random access memory while sixty-four megabytes of memory are addressable using the virtual memory addressing system.
  • Virtual memory systems accomplish this feat by providing memory management units which translate virtual memory addresses into physical memory addresses.
  • a particular physical address may be in main memory or in long term storage. If the physical address of information sought is in main memory, the information is accessed and utilized by the computer. If the physical address is in long term storage, the information is transferred to main memory where it may be used.
  • the basic memory management unit uses lookup tables which are stored in main memory. Any virtual address presented to the memory management unit is compared to the values stored in these tables to determine the physical address to access. There are often several levels of tables, and the comparison takes a great deal of system clock time.
  • cache memories which use very fast components to store recently used data and instructions. These cache memories are usually connected so that they are rapidly accessible to the processors. These caches are first looked to by a processor before going to main memory for any information. The theory of these caches is that information most recently used is more likely to be needed again before other information is needed. This theory is valid, and many systems using cache memories have hit rates of over ninety percent.
  • a typical memory management unit uses a translation lookaside buffer (TLB) to cache virtual page addresses which have been recently accessed along with their related physical page addresses.
  • TLB translation lookaside buffer
  • Such an address cache works on the same principle as do caches holding data and instructions, the most recently used addresses are more likely to be used than are other addresses.
  • the translation lookaside buffer furnishes a physical address for the information. If that physical address is in the related cache, then the information is immediately available to the processor without the necessity of going through the time consuming process of referring to the page lookup tables in main memory.
  • the memory management unit must retrieve the physical address using the lookup tables in main memory.
  • the physical address is recovered, it is stored along with the virtual address in the translation lookaside buffer so that the next time it is needed it is immediately available.
  • the information is recovered, it is stored in the cache under the physical address. This saves a great deal of time on the next use of the information because a typical lookup in the page tables may take from ten to fifteen clock cycles at each level of the search, while accessing the information using the translation lookaside buffer and the caches may require only one or two clock cycles.
  • U. S. patent application Serial No. 631,966 entitled TRANSLATION LOOKASIDE BUFFER, filed 21st December 1990 and assigned to the assignee of this invention, describes a translation lookaside buffer for a very fast RISC computer system which provides separate caches for data and for instructions. In a typical prior art computer system these different virtual addresses would be translated by separate hardware resources.
  • the translation lookaside buffer described stores virtual and physical addresses for data, instructions, and input/output operations.
  • Such a translation lookaside buffer allows the very rapid translation of all virtual addresses which might be used by a system with a very minimum amount of hardware. Such a system is well adapted to be used in a system in which most of the hardware is resident on a single chip.
  • an object of the present invention to provide an arrangement for speeding the operation of translating circuitry used for handling information from two individual sources which may provide information concurrently.
  • a translation lookaside buffer for caching virtual addresses from a plurality of sources along with the associated physical addresses which physical addresses must be rapidly accessible and in which virtual addresses may appear simultaneously from two of the sources requiring translation into physical addresses, comprising a primary cache for storing a plurality of individual virtual addresses and associated physical addresses from all of the plurality of sources, means for storing a single virtual address and its associated physical address from one of the plurality of sources which occurs most often each time a virtual address and an associated physical address from that one of the plurality of sources is referenced in the primary cache, and means for ascertaining whether the virtual address held in the means for storing a single virtual address and an associated physical address is a virtual address sought when an attempt is made to access the primary cache for a virtual address from the one of the plurality of sources and for another of the plurality of sources simultaneously.
  • Figure 1 is a block diagram of a translation lookaside buffer designed in accordance with the present invention.
  • the present invention relates to apparatus for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
  • the translation lookaside buffer 10 is a single relatively large cache of virtual address and their associated physical addresses.
  • the translation lookaside buffer 10 is utilized in a reduced instruction set computer (RISC) system which has both a data cache and an instruction cache and refers to both concurrently.
  • RISC reduced instruction set computer
  • the translation lookaside buffer 10 is the only such buffer in the system and thus stores addresses for both data and instructions.
  • this same translation lookaside buffer stores addresses used for input/output operations. Because a single translation lookaside buffer translates all of these addresses, the overall speed of address translation is substantially increased; and the area utilized for translation is substantially reduced. However, this particular architecture creates one problem which might otherwise slow the operation of translation.
  • the present invention provides a single register (called an instruction translation buffer register) which stores a single row of the translation lookaside buffer. In that register is placed the virtual address and the associated physical address for each instruction address translation accomplished by the translation lookaside buffer.
  • the instruction address is presented to the register for translation by the register and associated logic.
  • the instruction translation buffer register contains the physical page address of the last instruction which was translated. Because of the locality of instructions in a program (they tend to come from the same page), it is quite likely that the high bits of the virtual address being sought are identical to the high level virtual bits in the register and thus that the new virtual address will match the last. In fact, the instruction translation buffer register has been found to hold the physical address desired over ninety percent of the time. Consequently, the instruction address and a data address may be translated in parallel and the speed of operation of the machine maintained.
  • the virtual address sought by the system is presented on one of three sets of input lines 14, 15, or 16.
  • the address presented on the lines 14 is furnished by the input/output circuitry of the computer system.
  • the address presented on the lines 15 is an instruction address furnished by the integer processor of the computer system.
  • the address presented on the lines 16 is a data address furnished by the integer processor of the computer system.
  • the highest twenty bits of the virtual address sought are furnished to a portion 12 for comparison with the addresses stored therein.
  • the particular virtual address is furnished to the virtual tag section by a multiplexor 18 in response to a control signal designating the particular type of information sought.
  • an instruction in the integer processor designates the information sought as data or an instruction while the input/output circuitry indicates that the information sought is for input/output purposes.
  • a multiplexor 20 furnishes a context tag which is compared with the values in six context tag bit positions.
  • the context tag is furnished from a context register CXR 19 and is a value written by the memory management software.
  • both the virtual address tag and the context tag must match the bits sought for there to be a hit in the translation lookaside buffer 10.
  • the context tag is a group of bits which allows the system to select among a plurality of different groups of page tables which are used with different software programs. For any particular program being run on a system, the context tag remains the same throughout the program.
  • the context tag may be considered to be additional address bits.
  • the high order bits of a physical address are provided as output. These high order bits of each physical address have been previously stored in a portion 22 of the translation lookaside buffer 10 in the same row as the virtual address from which they are to be translated. These high order bits provide a physical page number from which a physical address may be obtained.
  • the low order bits of the virtual address and the physical address are the same and indicate the byte address within any particular page. Thus, the low order bits of the virtual address are combined with the physical page number, to provide a complete physical address.
  • the instruction translation buffer register 30 is provided.
  • the register 30 includes a number of bit positions sufficient to store the pertinent information from a row of the translation lookaside buffer 10.
  • the register 30 receives the instruction virtual address and its associated physical page address from the portions 12 and 22 of the translation lookaside buffer 10 as the translation of that instruction virtual address occurs. It may be seen that the bits of the virtual tag portion of the address are provided by the portion 12 via a series of conductors 32 while the bits of the physical page address portion of the address are provided by the portion 22 via a series of conductors 34. This information is then in the register 30 when the next instruction virtual address appears for translation.
  • the next instruction virtual address appears for translation, it is translated in the primary cache portions 12 and 22 of the translation lookaside buffer 10 so long as those portions are free. In this usual situation, the new instruction virtual address and its associated physical page address are placed in the register 30. However, when a instruction virtual cannot be translated in the primary cache of the translation lookaside buffer 10 because of another address translation having priority, the instruction virtual address on lines 15 vying for translation is transferred to a comparator 36. The comparator 36 compares the virtual address of the instruction sought with the last instruction virtual address stored in the register 30.
  • one or more of three multiplexors 38,39, or 40 is caused to transfer the physical page address to the processor for use.
  • the particular combination of the multiplexors 38,39, or 40 selected to transfer the address will depend on the size of the page being translated and has no significance so far as the present invention is concerned. In this manner, the instruction address and the data or input/output address may both be translated at the same time so that no delay in the pipeline of the processor occurs.
  • the failure to match is signalled to a state machine (not shown) at the output of the comparator 36.
  • the state machine in response to this signal causes the instruction virtual address to be retried at the translation lookaside buffer 10 at the next available time after the translation being processed. Since a miss is found to occur less than ten percent of the time and interference with the translation of an instruction virtual address occurs only about one third of the time, this delay will occur on an average less than once in every thirty instructions. As will be understood by those skilled in the art, this substantially increases the speed of operation of the system. More importantly, it does this without increasing the amount of hardware by any significant amount. Consequently, the system is able to be placed in the smallest possible area of silicon.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Claims (7)

  1. Tampon de traduction (10) destiné à mettre en oeuvre une opération d'antémémoire entre des adresses virtuelles pour des données et des instructions et des adresses physiques associées aux adresses virtuelles, dans lequel les adresses virtuelles pour les instructions et les données peuvent apparaítre sensiblement en même temps et nécessitent une traduction en adresses physiques, ledit tampon de traduction (10) comprenant :
    des moyens formant registre (30), pour stocker une adresse d'instruction virtuelle unique et son adresse physique associée à chaque fois qu'une adresse d'instruction virtuelle et une adresse physique associée est référencée dans l'antémémoire primaire (12, 22), et caractérisée par :
    une antémémoire primaire (12, 22) contenant une pluralité d'entrées, chaque entrée comportant une adresse de mémoire virtuelle (12), une adresse de mémoire physique correspondante (22) et une copie de données stockées par ladite mémoire à ladite adresse physique correspondante, lesdites entrées comportant des instructions (15), des données (16) et des adresses d'entrée/sortie (14) ; et
    des moyens de détermination (36), pour vérifier si l'adresse virtuelle contenue dans les moyens de registre (30) est une adresse virtuelle recherchée lorsqu'il est tenté d'accéder à l'antémémoire primaire pour une adresse virtuelle (12) avec deux adresses virtuelles reçues sensiblement en même temps.
  2. Tampon de traduction (10) selon la revendication 1, dans lequel les moyens formant registre (30) comprennent :
    un registre pour stocker une rangée unique de l'antémémoire primaire ; et
    des moyens (32) pour remplir le registre avec des informations provenant d'une rangée de l'antémémoire primaire (12) contenant l'adresse d'instruction virtuelle recherchée à chaque fois qu'une référence d'instruction d'adresse virtuelle apparaít.
  3. Tampon de traduction (10) selon la revendication 1, dans lequel les moyens de détermination (36) comprennent des moyens pour comparer l'adresse d'instruction virtuelle recherchée (15) et l'adresse d'instruction virtuelle stockée dans les moyens formant registre (30).
  4. Tampon de traduction (10) selon la revendication 1, comprenant en outre des moyens sensibles auxdits moyens de détermination (36) pour tenter d'accéder à l'antémémoire primaire avec l'adresse d'instruction virtuelle lorsque l'antémémoire primaire devient disponible.
  5. Tampon de traduction (10) selon la revendication 1, comprenant en outre :
    des moyens (18) pour accéder auxdites entrées à l'intérieur de ladite antémémoire primaire (12) avec des adresses de mémoire virtuelle pour retrouver lesdites données correspondant auxdites adresses de mémoire virtuelle, lesdits moyens (18) pour accéder à ladite antémémoire primaire (12) en donnant une priorité inférieure aux adresses d'instructions.
  6. Tampon de traduction (10) selon la revendication 1, comprenant en outre :
    lesdits moyens formant registre (30) pour stocker une adresse de mémoire virtuelle unique depuis ladite antémémoire primaire (12) et des données correspondant à ladite adresse de mémoire virtuelle ; et
    des moyens pour accéder auxdits moyens formant registre (30) avec une adresse de mémoire virtuelle, tandis que des moyens pour accéder audit tampon de traduction (10) accèdent sensiblement en même temps à ladite antémémoire primaire (12) avec une autre adresse de mémoire virtuelle, dans lequel lesdits moyens pour accéder audit tampon de traduction sont incapables d'accéder à ladite antémémoire primaire avec deux adresses de mémoire virtuelle sensiblement en même temps.
  7. Tampon de traduction (10) selon la revendication 5, comprenant en outre :
    le fait que lesdits moyens (18) pour accéder à ladite antémémoire primaire (12) comportent des moyens (32) pour accéder audit registre (30) avec une adresse virtuelle d'une instruction, tout en accédant sensiblement en même temps à l'antémémoire primaire (12) avec une adresse virtuelle de plus haute priorité, de façon que l'accès aux informations correspondant à ladite adresse virtuelle de ladite instruction ne soit pas sensiblement retardée en attendant la fin de l'accès à ladite antémémoire primaire avec ladite adresse virtuelle de plus haute priorité.
EP91311242A 1990-12-21 1991-12-03 Appareil pour augmenter le performance d'un tampon de traduction d'adresses Expired - Lifetime EP0492838B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/633,460 US5305444A (en) 1990-12-21 1990-12-21 Apparatus for increasing the number of hits in a translation lookaside buffer including instruction address lookaside register
US633460 1990-12-21

Publications (3)

Publication Number Publication Date
EP0492838A2 EP0492838A2 (fr) 1992-07-01
EP0492838A3 EP0492838A3 (en) 1993-01-13
EP0492838B1 true EP0492838B1 (fr) 1999-03-03

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EP91311242A Expired - Lifetime EP0492838B1 (fr) 1990-12-21 1991-12-03 Appareil pour augmenter le performance d'un tampon de traduction d'adresses

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US (1) US5305444A (fr)
EP (1) EP0492838B1 (fr)
JP (1) JP3449487B2 (fr)
KR (1) KR960001945B1 (fr)
CA (1) CA2058259C (fr)
DE (1) DE69130942T2 (fr)

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JP3802061B2 (ja) * 1995-03-03 2006-07-26 富士通株式会社 アドレス変換速度アップのための並列アクセスマイクロ−ｔｌｂ
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Also Published As

Publication number Publication date
CA2058259A1 (fr) 1992-06-22
DE69130942D1 (de) 1999-04-08
EP0492838A3 (en) 1993-01-13
JPH06180672A (ja) 1994-06-28
DE69130942T2 (de) 1999-09-30
KR960001945B1 (ko) 1996-02-08
JP3449487B2 (ja) 2003-09-22
US5305444A (en) 1994-04-19
CA2058259C (fr) 2002-12-17
EP0492838A2 (fr) 1992-07-01
KR920013135A (ko) 1992-07-28

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