EP0118553A1 - Durchgangsleitungsstruktur für dreidimensionale mikroelektronikanordnungen - Google Patents
Durchgangsleitungsstruktur für dreidimensionale mikroelektronikanordnungenInfo
- Publication number
- EP0118553A1 EP0118553A1 EP83903072A EP83903072A EP0118553A1 EP 0118553 A1 EP0118553 A1 EP 0118553A1 EP 83903072 A EP83903072 A EP 83903072A EP 83903072 A EP83903072 A EP 83903072A EP 0118553 A1 EP0118553 A1 EP 0118553A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- conductive path
- major surface
- substrate
- feedthrough structure
- feedthrough
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H10W20/021—
-
- H10W20/023—
-
- H10W20/20—
Definitions
- the invention relates to the structure of semi ⁇ conductor devices and particularly to the structure of microelectronic feedthroughs for three dimensional circuits.
- Feedthrough structures generally are well known.
- a common form of feedthrough is the thermal gradient zone melt (TGZM).
- TGZM thermal gradient zone melt
- U.S. patents Method of Making Deep Diodes, 3,901,736; Deep Diode Device and Method, 3,902,925; Deep Diode Devices and Method and Apparatus, 4,075,038; High Velocity Thermomigration Method of Making Deep Diodes, 3,898,106; The Stabilized Droplet Method of Making Deep Diodes Having Uniform Electrical Properties, 3,899,361; Method of Making Isolation Grids in Bodies of Semiconductor Material, 3,904,442; and Thermomigration of Metal-Rich Liquid Wires Through Semiconductor Materials, 3,899,362.
- Feedthroughs effected by the TGZM process typically have a cross sectional area on the order of one to two mils in diameter. Since no devices can be fabricated on the semiconductor surface occupied by the feedthrough, the presence of the feedthrough reduces the number of devices that can be placed on the semiconductor surface This result is contrary to the everpresent objective to increase the number and density of devices fabricated on a semiconductor device.
- the invention comprises a method and structure for reducing the surface area occupied by the end of the verticle feedthrough in a three dimensional semiconductor circuit device.
- a horizontal conducting path is laid down on a major surface of the substrate, with one end of the conducting path in electrical and physical contact with the feedthrough (e.g. a thermal gradient zone melt, TGZM).
- An epitaxial layer is then P ut down over the major surface covering the TGZM and burying the horizontal conducting path. Electrical contact is made to the other end of the buried horizontal conducting path by diffusion through the newly put down epitaxial layer, or by etching through the new epitaxial layer to the conducting path.
- the diffused region is of the same conductivity type as are the horizontal buried path and the TGZM.
- the cross sectional area of the diffusion region is 25 to 30 square microns compared to the 507 to 2027 square microns area of the TGZM. This results in substantial reduction of the surface area occupied by the ends of the TGZM feedthrough structure and allows more devices to be fabricated on the major surface of the semiconductor.
- FIG. 1 is a cross-sectional view of a section of a semiconductor substrate.
- FIG. 2 illustrates the placement of a feedthrough in the substrate.
- FIG. 3 shows the horizontal conducting means contacting one end of the feedthrough.
- FIG. 4 shows the addition of a thin epitaxial layer covering the feedthrough and horizontal conducting means.
- FIG. 5 shows the electrical connection between the horizontal conducting means and the top surface of the epitaxial layer.
- FIG. 1 shows a cross section of a small portion of semiconductor substrate 10.
- the substrate 10 has a first or top major surface 12 and a second or bottom major surface 14.
- Such a substrate may be stacked with others like it to form a high density three dimensional semiconductor device.
- active devices may be fabricated on both major surfaces 12 and 14 of substrate 10. In both cases it is often desirable to electrically connect a device on one substrate with a device on another substrate or to connect a device on a top major surface such as 12 with a device on a bottom major surface such as 14. Such interconnection is facilitated by the structure 20, as shown in FIG. 2, which comprises an electrically conductive path called a feedthrough. The feedthrough extends from one major surface 12 through the semiconductor substrate 10 to the other major surface 14.
- a semiconductor device on surface 12 may be electrically connected to a semi ⁇ conductor device on surface 14 by connecting the first device to the end 22 of feedthrough 20 lying on surface 12 and connecting the other device to the end 24 of feedthrough 20 which lies on surface 14.
- a semi ⁇ conductor device on surface 14 By connecting the first device to the end 22 of feedthrough 20 lying on surface 12 and connecting the other device to the end 24 of feedthrough 20 which lies on surface 14.
- the feedthrough structure is a convenient means to interconnect devices on opposite sides of a substrate, it does have the disadvantage of occupying substantial space on the major surfaces 12 and 14. Devices cannot be fabricated in the area occupied by the feedthrough nor in the small annular area surrounding the feedthrough. The total space lost can be significant if a number of feedthroughs are present in a single wafer.
- the feedthrough 20 will have a diameter of from 1 to 2 mils, i.e. an area of about 507 square microns to about 2027 square microns.
- a shallow conducting means such as conducting path 30 is fabricated in surface 12.
- the path 30 can be as long as desired and practical and the path may terminate in end 31 wherever convenient and compatible with the contemplated circuit.
- One end of path 30 must contact feedthrough 20 as shown at 32.
- the path 30 is electrically conductive, and of the same conductivity type as is feedthrough 20.
- a thin epitaxial layer 40 is applied as illustrated in FIG. 4 to cover the major surface 12, the end 22 of feedthrough 20, and the conducting path 30.
- Epitaxial layer 40 is of the same conductivity type as is substrate 10, and is relatively thin. The layer 40 may range from 0.5 to 20.0 microns in thickness.
- a conductive path 50 as shown in FIG. 5 is fabricated and extends from surface 42 to path 30. This path 50 may be formed by diffusion through the epitaxial layer 40.
- Path 50 is of the same conductivity as the TGZM and of opposite conductivity as the sub- strate 10. Typically, path 50 may be 5 microns square covering an area of about 25 square microns. This represents a significant decrease from the area of surface 12 occupied by the TGZM which was from 507 to 2027 square microns.
- the surface area of layer 40, located directly above feedthrough 20, is available for fabrication of semiconductor devices.
- the conductive path 50 is located at the distal end 31 of conductive path 30.
- path 30 could be tailored to place conductive path 50 at any desired location.
- all paths 30 on a given substrate could be made to terminate near the perimeter of the substrate. All paths 50 would correspondingly be located near the perimeter of the substrate, leaving the interior area of the substrate totally free of feedthrough connections. If preferred for a particuar application, paths 30 could be eliminated and paths 50 could be formed through layer 40 directly above (or below) the end 22 (or 24) of feedthrough 20. Such a path is shown as path 52 shown in broken lines in FIG. 5. In either case, the percentage of the surface area of surface 42 which is occupied by feedthrough structure is drastically reduced from the percentage of the surface area of surface 12 which is occupied by feedthrough structure. The per ⁇ centage reduction can be on the order of 2_00J2 or 98.7%.
- the substrate 10 will be 10 to 20 mils thick and comprised of a semiconductor of any type IV, type III-V, or type II-VI compound.
- the crystal orientation in silicon is normally ⁇ 100> for the feedthrough direction.
- the major surfaces 12 and 14 are ⁇ 100> oriented surfaces.
- conductive path 50 (and 52) shown extending from surface 42 to path 30 (or to feed- through 20) is shown as a diffused region.
- the conductive paths 50 or 52 could also be formed by etching through layer 40 by conventional techniques and providing a conductor also by conventional techniques, from surface 42 to path 30 (or feed ⁇ through 20).
- the spirit and scope of the invention are intended to be limited only by the appended claims.
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US41727682A | 1982-09-13 | 1982-09-13 | |
| US417276 | 1989-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0118553A1 true EP0118553A1 (de) | 1984-09-19 |
Family
ID=23653295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP83903072A Withdrawn EP0118553A1 (de) | 1982-09-13 | 1983-09-08 | Durchgangsleitungsstruktur für dreidimensionale mikroelektronikanordnungen |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0118553A1 (de) |
| IT (1) | IT8348952A0 (de) |
| WO (1) | WO1984001240A1 (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8900767A (nl) * | 1989-03-29 | 1990-10-16 | Philips Nv | Halfgeleiderinrichting met eendimensionale doteringsgeleiders en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting. |
| DE10205026C1 (de) * | 2002-02-07 | 2003-05-28 | Bosch Gmbh Robert | Halbleitersubstrat mit einem elektrisch isolierten Bereich, insbesondere zur Vertikalintegration |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2013735A1 (de) * | 1968-07-05 | 1970-04-10 | Gen Electric Inf Ita | |
| US3982268A (en) * | 1973-10-30 | 1976-09-21 | General Electric Company | Deep diode lead throughs |
| US4074342A (en) * | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
-
1983
- 1983-09-08 EP EP83903072A patent/EP0118553A1/de not_active Withdrawn
- 1983-09-08 WO PCT/US1983/001389 patent/WO1984001240A1/en not_active Ceased
- 1983-09-09 IT IT8348952A patent/IT8348952A0/it unknown
Non-Patent Citations (1)
| Title |
|---|
| See references of WO8401240A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1984001240A1 (en) | 1984-03-29 |
| IT8348952A0 (it) | 1983-09-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Designated state(s): DE FR GB |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 19840815 |
|
| RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: GAALEMA, STEVEN, D. Inventor name: GATES, JAMES, L. |