DK168417B1 - Method and system for synchronizing digital information signals - Google Patents

Abstract

The invention relates to a digital transmission system in which data words are transmitted in an error-correcting code. According to the invention, synchronisation words and the error rate of transmitted data words are evaluated jointly for the purpose of synchronisation. <IMAGE>

Description

in DK 168417 B1

The invention relates to a method and a system for synchronizing digital information signals as defined in the preamble of claim 1, respectively. the preamble of claim 10.

5 When transmitting information, signals are taken from an information source and supplied with a converter which converts the signals into electrical signals.

The electrical signals are passed to a transmitter which modulates the signals. Over an information channel 10, the modulated signals reach a receiving apparatus.

In the receiving apparatus, the signals are demodulated and fed to a transducer, which makes the data ascertainable to an information receiver. When transmitting digital signals, the digital signals on the receiver side of the transducer are processed by a decoder.

Such a transfer is described in NTZ, Vol. 36, 1983, booklet li. Here, the signals are transmitted from a satellite to a receiver by means of a phase shift coding (PSK) and decoded in the receiver. Data words are transmitted in an error-correcting code with sync words. In the synchronization, from an oscillation process, after successive synchronization words have been found, it is switched to a continuous operation in an oscillating state. In a time window, the frequency of the synchronization word is checked. Depending on the frequency of the sync word, it is decided whether to initiate a new oscillation process to search for a sync word for another time period. Voting means that the error rate of the synchronization word is allowed to be so high that a new oscillation process is first started for transfer errors that are no longer correctable or for total failure. This is far from unfavorable because a relationship must be established between disturbed synchronization words and disturbed data words, and this correlation must be reconciled so that the error rate in the synchronization word is first considered too high, if not the decoding of the data word results in exploitable signals.

The object of the invention is to improve the synchronization method, in particular synchronization words must be saved, the effective time for the data words must be extended and the signal-to-noise ratio must be increased.

This task is solved by the measures specified in claims 1 and 10. Advantageous further developments of the invention are set forth in the appended independent claims.

Since disruptions are uniformly distributed in the disturbed information channel, synchronization words and data words are disturbed uniformly. If the data words are transmitted in a code that independently corrects the data words, this correction is a measure of the disruption of the information channel. The number of corrections, ie. the number of correctable bits in a data word is thus a measure of a present disturbance in an information channel.

20 If a correction of the data words is no longer possible over a long period of time, the information channel can be described as totally disturbed.

The invention utilizes this realization and considers not only an interrupted synchronization word, but also the corrective data word, for assessing the interference from an information channel. A common assessment of error rates in the sync word and in the data word thus leads to a better decision criterion on a disruption in the information channel.

30 At the same time, the time needed to detect a disturbance can be reduced.

For a better understanding of the invention, the following is explained in greater detail on the basis of some exemplary embodiments and with reference to the drawing, in which fig. 1 shows an information system, FIG. 2 shows data sequences in an information system; FIG. 3 is a synchronization word recognition circuit; FIG. 4 shows another circuit for synchronization word-5 detection; FIG. 5 is a synchronization monitoring circuit; FIG. 6 is a circuit for performing concealments; FIG. 7 is a block diagram for synchronization word configuration; and FIG. 8 a circuit for switching between the oscillation process and the oscillating state.

FIG. 1 shows an information source 1, a transducer 2, a transmitter 3, an information channel 4, a disturbance 5, a receiver 6, a transducer 7, a decoder 8 for data words, a detector 9 for synchronization words, a monitoring unit 10 for the synchronization and an information receiver li. in transducer 7, data sequences are output to decoder 8 for data words and to detector 9 for synchronization words. In the oscillation process, the detector 9 searches for synchronization words. If the detector 9 detects synchronization words several times in a predetermined time frame, it switches to an inverted state. In the inverted state, both the data word decoder 8 and the synchronization word detector 9 monitor the synchronization. The monitoring unit 10 assesses both the frequency of the data words and the frequency of synchronization 30. If the receiver 6 is a 4-PSK demodulator, two subframes (channel A, channel B) are formed, hereinafter referred to as subframes, where both channels A, B are passed to decoder 8 and both channels A, B are passed to detector 9.

FIG. 2 shows data sequences with synchronization words 21, 22, 51 and 52 and with data words 23-50. In total, DK 168417 B1 4 contains 16 programs I-XVI with a left and a right channel L, R. The data words 23-30 and 37-44 contain the MSB (Most Significant Bit) values of the scan values. In the data words 31, 32 there are recorded parity bits (comparison bits) for error correction; in the data words 33, 34 extra information is recorded, e.g. a scale factor, and in the data words 35, 36, the Last Significant Bit (least significant bit) values are recorded of the scan values.

10 The scale factor is a coding indicating whether leading zeros in a data word 23-30, 37-44 are Tinder printed. The two channels A and B are extracted as subframes from a main frame during demodulation in a PSK demodulator.

Each of the two subframes (channel A, channel B) has an 11 bit sync word. The BCH redundancy 31, 32 (BCH = Bose Chaudhuri Hocquenghem) is a number of parity bits which optionally corrects the preceding data words 23, 25, 27, 29 respectively. 24, 26, 28, 30. This BCH code simultaneously indicates within certain limits that an error-correction is no longer possible. In this case, a consealment is performed. Consealment means the use of replacement values for incorrectly transmitted sampling values. If several (more than 3) erroneous scan values are transmitted consecutively, in 25 cases where sync values also occur falsified, this is a disrupted information channel, and thus a new oscillation process must be started.

FIG. 3 shows two buffer stores 61, 62, two matrices 63, 64, an OG link 65, a shift register 66, 30 a NAND link 67, a clock input 68 for a clock TF (clock sync word window), and a output 69. The data sequences channel A and channel B are displaced through the buffer bearings 61, 62. The matrices 63, 64 associated with the buffer bearings 61, 62 note the synchronization words. The matrices 63, 64 also detect the synchronization words if they contain an incorrect bit. For a single finding of two parallel synchronization words in the two subframes of channel A and channel B, a flag bit (state bit) is set in the shift register 66. In the inverted state, the shift register 66 is always started over the input 68 with the clock signal TF and thus the flag bit set when a sync word is expected to be found. The number of outputs Q1-Q4 indicates how many parallel synchronization words must be serially dropped before the synchronization over the NAND link 67 on the output 69 is indicated as no longer present.

FIG. 4 shows a further example of synchronization word detection. In a switch register 71, the set value of a synchronization word is loaded. Synchronization words arriving across channels A 15 and B are stored in buffer stores 61 and 62. In comparator 72 and 73, the synchronization words are compared bit by bit with the setpoint. Incorrect bits are added in a NAND link 74 and counted in an error counter 75. Above a NOR link 76, the number of errors is interrogated. The query is triggered over the input ABFN (query - error in negative logic) after utilizing the last synchronization word bit. The output QSY (synchronization output) indicates whether the synchronization words have been detected. The sync words are considered if a predetermined number of erroneous bits, e.g. 2, not exceeded.

FIG. 5 shows an OR link 81, over which the flag bit is put in a shift register (66). A flag bit is set if a sync word has been detected, or if a data word has been found error-free or with correctable errors. Only when a synchronization word is dropped or a multi-error synchronized word and a persistent data word error is the flag bit not set. The persistent errors 35 in the data word find the coupling 83 for error correction. The message of the persistent errors is delivered over a negator 82 to the OR link 81.

DK 168417 B1 6

FIG. 6 shows a coupling 83 for error correction, buffer bearings 84, 85 and 86, a mean value coupling 87, a switch 88, a disconnector 89, data lines 90-95 and control lines 96 and 97. In the buffer bearings 84-86, consecutive data words are stored. ATW n + 1, enough - 1 (scanning values n + 1, enough - 1). If the scan value n of the error correction circuit is found to be error free or error correctable, the scan value n over 10 data line 90 and switch 88 is output to the output ATW '. If a sensing value n is found to be no longer correctable, from the previous sensing value n - 1 and the subsequent value n + 1, a mean value is generated in the coupling 87 and this mean value 15 is supplied via the switch 88 to the output ATW '. If several sensing values are found to be non-correctable one after the other, it must not be deleted as error-free and in the buffer storage 86 intermediate value. The control line 97 controls the switch 89 such that 20 at several successive uncorrectable sensing values reaches no uncorrectable sensing value into the buffer storage 86, and the last yet usable value remains in the buffer storage 86. If several uncorrectable sensing values follow one after the other, 25 becomes the last usable one. sensing value over line 91 and switch 88 delivered to output ATW 'until an error-free or correctable value is obtained. For the mean value formation in the coupling 87, the last usable sensing value which is retained in the buffer storage 86 is used, and the subsequent first again error-free, respectively. corrected value and they are delivered to the output ATW '. As the next value, the new error-free value is supplied to the output ATW '. Control lines 96 and 97 control switch 88.

DK 168417 B1 7

A table shows the effect of the one shown in FIG. 3 (R »right, F = wrong).

5 1. BF X. BF ATWn + l ATWn ATWn-1 ATW

No No R R R ATWn

No No F R R ATWn

Yes No R F R (ATWn + l + ATWn-1) x 1/2 10 No No F R F ATWn

No Yes F F R ATWn-1

Yes No R F R (ATWn + 1 + ATWn-1) x 1/2

No No R R F ATWn 15 In line 1 of the table, the scan value ATWn is delivered to the output ATW 'if the key values ATWn + 1, ATWn and ATWn-1 in buffer bearings 84-86 are error free or corrected. Then the control lines 96 and 97 (1st BF and X. BF) are set to low. In line 2, the scan value ATWn is again fed to the output ATW ', even though the scan value ATWn + 1 is uncorrected. If, as line 3 shows, a sample value ATWn with uncorrected error is intermediate stored in buffer memory 85, but error-free or corrected values are intermediate stored in buffer memory 84 and 86, the mean value generated by the key values ATWn + 1 and ATWn-1 is supplied. , to the output ATW '. Line 4 shows that an error-free or corrected scan value contained in buffer memory 85 reaches the output ATW ', 30 even if buffer memories 84 and 86 contain uncorrectable values. Line 5 shows that the last usable scan value ATWn-1 is retained in buffer storage 86 and is output to the output ATW 'if uncorrected values arrive in buffer stores 84 and 85. Li-35 nie 3 and 6 are the same. Line 7 shows that if a faulty or corrected data word is in buffer storage 85, coupler 89 must be re-coupled.

DK 168417 B1 8

In a 4-PSK demodulation, two parallel bits are extracted for each transmitted information unit. These two parallel bits are distributed on channels A and B. In the PSK demodulation, phase errors occur, which in case of differential demodulation results in a double fault. Double error means that two consecutive bits are decoded incorrectly. In the event of a faulty demodulation, an error in channel A automatically deducts an additional error in channel A or an error in channel B. Therefore, it is advantageous if during the oscillation process of the synchronization word finding, no one synchronization word per check is checked. subframe but on sync half.

FIG. 7 shows a block diagram of the sync word statement. Over channels A and B, buffer stores 61 and 62 are loaded with synchronization words. In matrix arrays 101 and 102, synchronization halves are detected, respectively. sought. The process is referred to as the search process. Matrix array 101 20 checks the first ten or twelve bits in both parallel synchronization words, and matrix array 102 controls the last ten or twelve bits in both synchronization words (1 sync word = 11 bit, 1 sync half = 5 or 6 bit, two parallel sync words = 22 bits, 2 parallel synchronization halves = 10 or 12 bits). During the oscillation process, two synchronization halves are sufficient to enable a frame bit counter 105 over a coupler 103. Advantageously, the frame bit counter 105 30 over a switch 104 causes an error check of the newly received synchronization words. The error check with the shift register 71, the comparator links 72, 73, or link 74 and the error counter 75 has already been described with reference to FIG. 4. The frame bit counter 105 and 35 couplers 103 and 104 cooperate so that during the oscillation process, synchronization halls are detected and switched to circuit parts 71-75 for synchronization wording. It is switched to the inverted state after finding a synchronization halfword and after finding two consecutive parallel synchronization words. In the inverted state, the result of checking synchronization halves in matrix arrays 101, 102 is waived. If a synchronization word is expected, the frame bit counter 105 leaves the shift register with the 10 setpoint and, at the end of a synchronization word, switches the control over the ABFN line. of the counter 75 to the output QSY. At the same time, the frame bit counter performs a back scramble. Among other things. is performed due to synchronization difficulties in the receiver which trigger an uninterrupted series of zeros or an uninterrupted series of afters, a scrambling in such a way that there are always enough shifts from zero to one and from one to zero to ensure a clock synchronization on the receiver side. In addition, there are 20 on the receiver side a descrambler (back scrambler) and on the transmitter side a scrambler.

FIG. 8 shows the shift register 66, a NOR link 67, an input 68 for a signal TF, an output 69 for a signal SSU (search synchronization word), inputs 25 for signals QSY and stop and the negative BF signal, an OR link 81 , negators 111 and 112, NOR joints 113 and 114, a D-FF (Delay-Flip-Flop) 115, an OG joint 116 and an exit SA. Above the input SI, flag bits are inserted in the shift register 66. These flag-30 bits indicate whether there is a synchronization. In the inverted state, the AND link 116 is decoupled over the stop input, and over the OR link 81, a flag bit can be set if a data word is error-free or error-corrected, or if two parallel synchronization words are found. During the oscillation process, the OG joint is blocked from the stop entrance,

Claims (16)

A method for synchronizing digital information signals in a receiver (6,7), in particular for satellite radio, where synchronization words (21,22,51,52) and data words (23-50) are transmitted in regular time sections 30 (main frames) where the synchronization words and / or the data words have constant password length and where the data transfer uses an error-correcting code (BCH) in which, during a swivel process, a search process is started to look up the sync words and in a swivel state is switched to a synchronization monitor, characterized by, that DK 168417 B1 11 synchronization monitoring utilizes a control of the synchronization words (21,22,51,52) and a check of the frequency of transmitted data words (23-50), that in the inverted state switches to resynchronization 5 when a data word does not can be further corrected and a number of consecutive sync words recognized as being incorrect and that during the search process, It is preferable to find a sync word quickly, preferably only parts of a sync word are controlled, for example, sync half word. Method according to claim 1, characterized in that the inverted state is maintained if there is a limited number of errors in the synchronization words (21,22,51,52). Method according to claim 1, characterized in that the inverted state is maintained if a limited number of consecutive synchronization words (21,22,51,52) falls out. Method according to claim 1, characterized in that the inverted state is maintained if a limited number of consecutive synchronization words (21,22,51,52) contains a limited number of errors and / or falls out. Method according to one or more of the preceding claims, characterized in that the inverted state is maintained if one or more uncorrected data words (23-50) are received. Method according to claim 5, characterized in that one or more inaccurate data words (23-50) carry out one or more concealments (Fig. 6). Method according to one or more of the preceding claims, characterized in that the shifting process is switched to the inverted state if two or more synchronizing words (21,22,51,52) are in succession in regular time sections. DK 168417 B1 12 Method according to one or more of the preceding claims, characterized in that the switching process is switched to the swung state if synchronization words (21,22,51,52) are received once or several times after each other and / or error-free or error-correctable data words (23-50). Method according to claim 7 or 8, characterized in that a limited number of errors in the synchronization words (21,22,51,52) are allowed. 10. System for synchronizing digital information signals in a receiver (6, 7), in particular for satellite radio, where synchronization words (21,22,51,52) and data words (23-50) are transmitted in regular time sections (main frames), where the synchronization words and / or then 15 words have a constant password length and a data correction code (BCH) is used for data transfer, where a swivel process starts a search process to look up the sync words and in a swung state switches to a syn -20 synchronization monitoring, in accordance with the method according to claim 1, characterized in that a synchronization monitoring unit (10) for controlling the synchronization words (21, 22, 51, 52) with a synchronization detector (9) and with a data word decoder 25 (8) is provided. for checking the frequency of the transmitted data words (23-50), the synchronization word detector (9) includes a coupling (61, 62, 63, 64, 65; 101, 102, 103) for recognizing synchronization and, in the inverted state, switch to resynchronization, 30 when a data word can no longer be corrected and a number of consecutive synchronization words in the decoder (9) is recognized as being incorrect. System according to claim 10, characterized in that a switch register (66) stores the state of 35 error rates in the synchronization words and / or data words in the last n time sections (main frames). DK 168417 B1 13 System according to claim 10 or 1, characterized in that a coupling (83) exists for error correction. System according to claim 12, characterized in that the coupling (83) controls a coupling (84,89) for forming concealments. System according to any one of claims 10-13, characterized in that a flip-flop (115) stores the state of the oscillation process or the state of the oscillation 10. System according to any one of claims 10-14, characterized in that there is a frame bit counter (105) which counts the number of bits in the frames. System according to any one of claims 10-15, characterized in that the frame bit counter (105) performs a back-scrambling.