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DE69828074D1 - Direkt-speicherzugriff / transaktionen auf ein bus mit niedriger pinanzahl - Google Patents

Direkt-speicherzugriff / transaktionen auf ein bus mit niedriger pinanzahl

Info

Publication number
DE69828074D1
DE69828074D1 DE1998628074 DE69828074T DE69828074D1 DE 69828074 D1 DE69828074 D1 DE 69828074D1 DE 1998628074 DE1998628074 DE 1998628074 DE 69828074 T DE69828074 T DE 69828074T DE 69828074 D1 DE69828074 D1 DE 69828074D1
Authority
DE
Germany
Prior art keywords
transactions
bus
memory access
direct memory
low pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1998628074
Other languages
English (en)
Other versions
DE69828074T2 (de
Inventor
H Gafken
A Bennett
I Poisner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69828074D1 publication Critical patent/DE69828074D1/de
Publication of DE69828074T2 publication Critical patent/DE69828074T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE69828074T 1997-09-24 1998-06-26 Direkt-speicherzugriff / transaktionen auf ein bus mit niedriger pinanzahl Expired - Lifetime DE69828074T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US936318 1997-09-24
US08/936,318 US6157970A (en) 1997-09-24 1997-09-24 Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
PCT/US1998/013402 WO1999015949A1 (en) 1997-09-24 1998-06-26 Direct memory access (dma) transactions on a low pin count bus

Publications (2)

Publication Number Publication Date
DE69828074D1 true DE69828074D1 (de) 2005-01-13
DE69828074T2 DE69828074T2 (de) 2005-12-22

Family

ID=25468468

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69828074T Expired - Lifetime DE69828074T2 (de) 1997-09-24 1998-06-26 Direkt-speicherzugriff / transaktionen auf ein bus mit niedriger pinanzahl

Country Status (7)

Country Link
US (1) US6157970A (de)
EP (1) EP1021756B1 (de)
KR (1) KR100352224B1 (de)
CN (1) CN1126015C (de)
AU (1) AU8377098A (de)
DE (1) DE69828074T2 (de)
WO (1) WO1999015949A1 (de)

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US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US6763452B1 (en) 1999-01-28 2004-07-13 Ati International Srl Modifying program execution based on profiling
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US8065504B2 (en) 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
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CN202177894U (zh) * 2011-07-14 2012-03-28 鸿富锦精密工业（深圳）有限公司 主板故障诊断卡
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Also Published As

Publication number Publication date
KR20010024260A (ko) 2001-03-26
KR100352224B1 (ko) 2002-09-12
WO1999015949A1 (en) 1999-04-01
DE69828074T2 (de) 2005-12-22
US6157970A (en) 2000-12-05
AU8377098A (en) 1999-04-12
EP1021756A4 (de) 2000-12-20
HK1028459A1 (en) 2001-02-16
EP1021756B1 (de) 2004-12-08
CN1301361A (zh) 2001-06-27
EP1021756A1 (de) 2000-07-26
CN1126015C (zh) 2003-10-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806