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DE69816784D1 - Prozessorbefehl mit Hashcodierung - Google Patents

Prozessorbefehl mit Hashcodierung

Info

Publication number
DE69816784D1
DE69816784D1 DE69816784T DE69816784T DE69816784D1 DE 69816784 D1 DE69816784 D1 DE 69816784D1 DE 69816784 T DE69816784 T DE 69816784T DE 69816784 T DE69816784 T DE 69816784T DE 69816784 D1 DE69816784 D1 DE 69816784D1
Authority
DE
Germany
Prior art keywords
processor command
hash coding
hash
coding
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69816784T
Other languages
English (en)
Other versions
DE69816784T2 (de
Inventor
Costas Calamvokis
Aled Justin Edwards
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69816784D1 publication Critical patent/DE69816784D1/de
Publication of DE69816784T2 publication Critical patent/DE69816784T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
DE69816784T 1998-05-01 1998-05-01 Prozessorbefehl mit Hashcodierung Expired - Lifetime DE69816784T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98303431A EP0953897B1 (de) 1998-05-01 1998-05-01 Prozessorbefehl mit Hashcodierung

Publications (2)

Publication Number Publication Date
DE69816784D1 true DE69816784D1 (de) 2003-09-04
DE69816784T2 DE69816784T2 (de) 2004-04-15

Family

ID=8234805

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69816784T Expired - Lifetime DE69816784T2 (de) 1998-05-01 1998-05-01 Prozessorbefehl mit Hashcodierung

Country Status (3)

Country Link
US (1) US6272614B1 (de)
EP (1) EP0953897B1 (de)
DE (1) DE69816784T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE9904685D0 (sv) 1999-12-17 1999-12-17 Switchcore Ab A programmable packet decoder
JP3729064B2 (ja) * 2000-11-29 2005-12-21 日本電気株式会社 データ依存関係検出装置
CN100533410C (zh) * 2001-08-27 2009-08-26 英特尔公司 通用执行数据通路中软件控制的内容可寻址存储器
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7111305B2 (en) * 2002-10-31 2006-09-19 Sun Microsystems, Inc. Facilitating event notification through use of an inverse mapping structure for subset determination
US20040103399A1 (en) * 2002-11-22 2004-05-27 Manisha Agarwala Data trace compression map
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US20080317245A1 (en) * 2007-06-20 2008-12-25 Franny Wei Hash function implemention with ROM and CSA
JP2021157604A (ja) * 2020-03-27 2021-10-07 株式会社村田製作所 データ通信装置、データ通信モジュール

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2148652B (en) 1983-09-15 1987-09-09 Sinclair Res Ltd Television receivers
GB8327567D0 (en) * 1983-10-14 1983-11-16 Gen Electric Co Plc Computers
US5170475A (en) * 1989-03-06 1992-12-08 Motorola, Inc. Data processor having instructions for interpolating between memory-resident data values respectively
US5333283A (en) * 1991-10-29 1994-07-26 International Business Machines Corporation Case block table for predicting the outcome of blocks of conditional branches having a common operand
US5754806A (en) * 1995-11-03 1998-05-19 Holtek Microelectronics, Inc. Memory table look-up device and method

Also Published As

Publication number Publication date
DE69816784T2 (de) 2004-04-15
EP0953897A1 (de) 1999-11-03
US6272614B1 (en) 2001-08-07
EP0953897B1 (de) 2003-07-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE