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DE69634464D1 - Cachespeicher - Google Patents

Cachespeicher

Info

Publication number
DE69634464D1
DE69634464D1 DE69634464T DE69634464T DE69634464D1 DE 69634464 D1 DE69634464 D1 DE 69634464D1 DE 69634464 T DE69634464 T DE 69634464T DE 69634464 T DE69634464 T DE 69634464T DE 69634464 D1 DE69634464 D1 DE 69634464D1
Authority
DE
Germany
Prior art keywords
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69634464T
Other languages
English (en)
Other versions
DE69634464T2 (de
Inventor
Peter Cumming
Richard Grisenthwaite
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Inc filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69634464D1 publication Critical patent/DE69634464D1/de
Publication of DE69634464T2 publication Critical patent/DE69634464T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69634464T 1995-10-26 1996-10-23 Cachespeicher Expired - Lifetime DE69634464T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9521977.0A GB9521977D0 (en) 1995-10-26 1995-10-26 Cache memory
GB9521977 1995-10-26

Publications (2)

Publication Number Publication Date
DE69634464D1 true DE69634464D1 (de) 2005-04-21
DE69634464T2 DE69634464T2 (de) 2006-01-05

Family

ID=10782960

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69634464T Expired - Lifetime DE69634464T2 (de) 1995-10-26 1996-10-23 Cachespeicher

Country Status (4)

Country Link
US (1) US5946705A (de)
EP (1) EP0770955B1 (de)
DE (1) DE69634464T2 (de)
GB (1) GB9521977D0 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6112299A (en) * 1997-12-31 2000-08-29 International Business Machines Corporation Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching
US6101573A (en) * 1998-06-12 2000-08-08 Arm Limited Bit line and/or match line partitioned content addressable memory
US6725337B1 (en) * 2001-05-16 2004-04-20 Advanced Micro Devices, Inc. Method and system for speculatively invalidating lines in a cache
KR100591769B1 (ko) * 2004-07-16 2006-06-26 삼성전자주식회사 분기 예측 정보를 가지는 분기 타겟 버퍼
JP4393317B2 (ja) * 2004-09-06 2010-01-06 富士通マイクロエレクトロニクス株式会社 メモリ制御回路
US7640399B1 (en) 2006-05-10 2009-12-29 Advanced Micro Devices, Inc. Mostly exclusive shared cache management policies
JP4940824B2 (ja) * 2006-08-18 2012-05-30 富士通セミコンダクター株式会社 不揮発性半導体メモリ

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781812A (en) * 1971-06-28 1973-12-25 Burroughs Corp Addressing system responsive to a transfer vector for accessing a memory
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
DE69127936T2 (de) * 1990-06-29 1998-05-07 Digital Equipment Corp Busprotokoll für Prozessor mit write-back cache
DE4211222B4 (de) * 1991-04-05 2009-05-28 Kabushiki Kaisha Toshiba, Kawasaki Abzweigungs-Vorhersage-Vorrichtung und Abzweigungs-Vorhersage-Verfahren für einen Super-Skalar-Prozessor
GB9205551D0 (en) * 1992-03-13 1992-04-29 Inmos Ltd Cache memory
US5692167A (en) * 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
EP0649084A1 (de) * 1993-10-18 1995-04-19 Cyrix Corporation Verzweigungsverarbeitung in Mikroprozessor
US5604909A (en) * 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
US5550995A (en) * 1994-01-03 1996-08-27 Motorola, Inc. Memory cache with automatic alliased entry invalidation and method of operation
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer

Also Published As

Publication number Publication date
US5946705A (en) 1999-08-31
EP0770955B1 (de) 2005-03-16
GB9521977D0 (en) 1996-01-03
DE69634464T2 (de) 2006-01-05
EP0770955A1 (de) 1997-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition