[go: up one dir, main page]

DE69620351D1 - Phasenregelschleife im Empfänger zur Zurückgewinnung eines zum Sender synchronen Taktes - Google Patents

Phasenregelschleife im Empfänger zur Zurückgewinnung eines zum Sender synchronen Taktes

Info

Publication number
DE69620351D1
DE69620351D1 DE69620351T DE69620351T DE69620351D1 DE 69620351 D1 DE69620351 D1 DE 69620351D1 DE 69620351 T DE69620351 T DE 69620351T DE 69620351 T DE69620351 T DE 69620351T DE 69620351 D1 DE69620351 D1 DE 69620351D1
Authority
DE
Germany
Prior art keywords
transmitter
recovery
receiver
locked loop
phase locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69620351T
Other languages
English (en)
Other versions
DE69620351T2 (de
Inventor
Rokugo Yoshinori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69620351D1 publication Critical patent/DE69620351D1/de
Publication of DE69620351T2 publication Critical patent/DE69620351T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE69620351T 1995-11-20 1996-11-15 Phasenregelschleife im Empfänger zur Zurückgewinnung eines zum Sender synchronen Taktes Expired - Fee Related DE69620351T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30105695A JP2891149B2 (ja) 1995-11-20 1995-11-20 位相制御ループ方式

Publications (2)

Publication Number Publication Date
DE69620351D1 true DE69620351D1 (de) 2002-05-08
DE69620351T2 DE69620351T2 (de) 2002-11-14

Family

ID=17892337

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620351T Expired - Fee Related DE69620351T2 (de) 1995-11-20 1996-11-15 Phasenregelschleife im Empfänger zur Zurückgewinnung eines zum Sender synchronen Taktes

Country Status (5)

Country Link
US (1) US5864248A (de)
EP (1) EP0776094B1 (de)
JP (1) JP2891149B2 (de)
AU (1) AU724025B2 (de)
DE (1) DE69620351T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3092660B2 (ja) 1997-12-19 2000-09-25 日本電気株式会社 ランダムな時刻情報から基準クロックを再生するｐｌｌとその方法
JP3444397B2 (ja) * 1998-02-06 2003-09-08 ヤマハ株式会社 ディジタル信号受信装置、方法、および該方法に係るプログラムを記憶した記憶媒体
US20030053578A1 (en) * 2001-09-18 2003-03-20 Sun Microsystems, Inc. Synchronous receiver
US7043651B2 (en) * 2001-09-18 2006-05-09 Nortel Networks Limited Technique for synchronizing clocks in a network
GB2387516B (en) * 2002-04-11 2005-03-09 Cambridge Broadband Ltd Communication system
US20040047335A1 (en) * 2002-06-21 2004-03-11 Proctor James Arthur Wireless local area network extension using existing wiring and wireless repeater module(s)
US7020791B1 (en) * 2002-09-19 2006-03-28 Nortel Networks Limited Clock recovery using a double-exponential smoothing process
US7512203B2 (en) * 2005-03-30 2009-03-31 Silicon Laboratories Inc. Data cleaning with an asynchronous reference clock
WO2006113986A1 (en) * 2005-04-23 2006-11-02 Nortel Networks Limited Method and apparatus for designing a pll
DE102007054201B4 (de) 2007-11-12 2012-10-11 Atmel Automotive Gmbh Empfangsschaltkreis, Verwendung einer digitalen PLL-Struktur und Verfahren zum Empfangen eines Signals einer Frequenzumtastung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3944940A (en) * 1974-09-06 1976-03-16 Pertec Corporation Versatile phase-locked loop for read data recovery
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
JP2861515B2 (ja) * 1991-07-29 1999-02-24 日本電気株式会社 パケット網における送受信間クロック同期方式及びクロック同期装置
JP2959225B2 (ja) * 1991-08-07 1999-10-06 日本電気株式会社 ディジタルデータ送信装置及びそれを用いた送受信システム
US5390180A (en) * 1991-10-10 1995-02-14 Nec America, Inc. SONET DS-N desynchronizer
ATE180931T1 (de) * 1992-10-02 1999-06-15 Siemens Ag Filter zur einstellung der bandbreite eines regelkreises
JP2518148B2 (ja) * 1993-03-12 1996-07-24 日本電気株式会社 クロック従属同期方法
JP2818997B2 (ja) * 1993-06-30 1998-10-30 シャープ株式会社 ディジタルデータ検出器
JPH0766814A (ja) * 1993-08-24 1995-03-10 Anritsu Corp Ａｔｍクロック再生装置
US5612981A (en) * 1994-02-15 1997-03-18 Philips Electronics North America Corporation Apparatus and methods for improving timing recovery of a system clock
KR970003097B1 (ko) * 1994-12-02 1997-03-14 양승택 다단 제어구조를 갖는 고속 비트동기 장치
US5486792A (en) * 1995-03-06 1996-01-23 Motorola, Inc. Method and apparatus for calculating a divider in a digital phase lock loop

Also Published As

Publication number Publication date
EP0776094A1 (de) 1997-05-28
DE69620351T2 (de) 2002-11-14
JPH09149016A (ja) 1997-06-06
EP0776094B1 (de) 2002-04-03
AU7184796A (en) 1997-05-29
US5864248A (en) 1999-01-26
AU724025B2 (en) 2000-09-07
JP2891149B2 (ja) 1999-05-17

Similar Documents

Publication Publication Date Title
GB2296396B (en) Clock pulse generation and recovery using a phase locked loop
EP0661842A3 (en) Clock recovery using gated phase lock loop.
DE69620351D1 (de) Phasenregelschleife im Empfänger zur Zurückgewinnung eines zum Sender synchronen Taktes
CA2302370A1 (en) System and method for high-speed, synchronized data communication
ZA927386B (en) A digital transmission system including a receiver that performs coherent demodulation directly at microwave fraquency.
DE69909852D1 (de) Digitale Phasenregelschleife zur Verminderung des Jitters
DE60141867D1 (de) Verfahren zum synchronisieren von daten
CA2001018A1 (en) Power conservation method and apparatus for a portion of a synchronous information signal
EP0244122A3 (en) Clock recovery digital phase-locked loop
DE69633084D1 (de) Taktrückgewinnung in einem netzwerksynchronisiertem Modem
DE69226283D1 (de) Phasenverschiebung eines taktsignals, im besonderen zur taktwiedergewinnung eines digitalen datensignals
CA2066037A1 (en) Digital phase-locked loop biphase demodulating method and apparatus
EP0413153A3 (en) Quadrature phase demodulation using a training sequence and a local signal offset from the received carrier frequency
WO2004051887A3 (en) Method for synchronizing communication units in a synchronous wireless communication
EP0521525A3 (en) Delay demodulation method, for dpsk, insensitive to carrier frequency offsets
DE3673878D1 (de) Verfahren und anordnung fuer verringerung des phasenzitterns einer synchronen digitalen impulsfolge zur taktwiedergewinnung.
GB2253749B (en) Method for fast frequency acquisition in a phase locked loop
WO1998052284A3 (en) Phase detector arrangement
DE60019032D1 (de) Gesteuerter Oszillator in einem Netzwerk zur Taktrückgewinnung von digitalen Symbolen
DE69117287D1 (de) Verfahren zur rückgewinnung von erdgas in form einer unter normalbedingungen flüssigen, kohlenstoff enthaltende verbindung
DE69832674D1 (de) Phasenregelkreis und Verfahren zur Rückgewinnung eines Taktsignals
AU646375B2 (en) Phase locked loop for extracting clock pulses through wave differential method
FI940706L (fi) Menetelmä vastaanottimen synkronoimiseksi vastaanotetun signaalin taajuuteen ja vaiheeseen
ATE179851T1 (de) Mpsk-demodulator
GB2291293B (en) Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee