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DE69616903D1 - Mehrprozessoranordnung und Verfahren zur Synchronisierung zwischen Prozessoren - Google Patents

Mehrprozessoranordnung und Verfahren zur Synchronisierung zwischen Prozessoren

Info

Publication number
DE69616903D1
DE69616903D1 DE69616903T DE69616903T DE69616903D1 DE 69616903 D1 DE69616903 D1 DE 69616903D1 DE 69616903 T DE69616903 T DE 69616903T DE 69616903 T DE69616903 T DE 69616903T DE 69616903 D1 DE69616903 D1 DE 69616903D1
Authority
DE
Germany
Prior art keywords
synchronization
processors
multiprocessor arrangement
multiprocessor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69616903T
Other languages
English (en)
Other versions
DE69616903T2 (de
Inventor
Takeshi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69616903D1 publication Critical patent/DE69616903D1/de
Publication of DE69616903T2 publication Critical patent/DE69616903T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE69616903T 1995-08-10 1996-08-09 Mehrprozessoranordnung und Verfahren zur Synchronisierung zwischen Prozessoren Expired - Fee Related DE69616903T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7204148A JPH0950400A (ja) 1995-08-10 1995-08-10 マルチプロセッサシステム

Publications (2)

Publication Number Publication Date
DE69616903D1 true DE69616903D1 (de) 2001-12-20
DE69616903T2 DE69616903T2 (de) 2002-07-18

Family

ID=16485637

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69616903T Expired - Fee Related DE69616903T2 (de) 1995-08-10 1996-08-09 Mehrprozessoranordnung und Verfahren zur Synchronisierung zwischen Prozessoren

Country Status (5)

Country Link
US (1) US5923855A (de)
EP (1) EP0758772B1 (de)
JP (1) JPH0950400A (de)
CA (1) CA2182841C (de)
DE (1) DE69616903T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09204403A (ja) * 1996-01-26 1997-08-05 Hitachi Ltd 並列計算機
US6314495B1 (en) * 1998-01-07 2001-11-06 International Business Machines Corporation Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations
US6272593B1 (en) 1998-04-10 2001-08-07 Microsoft Corporation Dynamic network cache directories
US8028318B2 (en) 1999-07-21 2011-09-27 Touchtunes Music Corporation Remote control unit for activating and deactivating means for payment and for displaying payment status
JP3550092B2 (ja) * 1998-12-10 2004-08-04 富士通株式会社 キャッシュ装置及び制御方法
US6286082B1 (en) * 1999-04-19 2001-09-04 Sun Mocrosystems, Inc. Apparatus and method to prevent overwriting of modified cache entries prior to write back
US6553409B1 (en) * 1999-07-09 2003-04-22 Microsoft Corporation Background cache synchronization
US7181539B1 (en) * 1999-09-01 2007-02-20 Microsoft Corporation System and method for data synchronization
CN1264091C (zh) * 1999-11-22 2006-07-12 阿茨达科姆公司 分布式高速缓存同步协议
KR100394827B1 (ko) * 1999-12-22 2003-08-21 엘지전자 주식회사 이동통신교환기의 프로세서 재시동을 위한 프로그램 및데이터 적재방법
US6615281B1 (en) * 2000-05-05 2003-09-02 International Business Machines Corporation Multi-node synchronization using global timing source and interrupts following anticipatory wait state
US6651145B1 (en) * 2000-09-29 2003-11-18 Intel Corporation Method and apparatus for scalable disambiguated coherence in shared storage hierarchies
JP4085389B2 (ja) * 2003-12-24 2008-05-14 日本電気株式会社 マルチプロセッサシステム、マルチプロセッサシステムにおける一貫性制御装置及び一貫性制御方法
TW200717246A (en) * 2005-06-24 2007-05-01 Koninkl Philips Electronics Nv Self-synchronizing data streaming between address-based producer and consumer circuits
US7587555B2 (en) * 2005-11-10 2009-09-08 Hewlett-Packard Development Company, L.P. Program thread synchronization
US7555607B2 (en) * 2005-11-10 2009-06-30 Hewlett-Packard Development Company, L.P. Program thread syncronization for instruction cachelines
US20090319804A1 (en) * 2007-07-05 2009-12-24 Broadcom Corporation Scalable and Extensible Architecture for Asymmetrical Cryptographic Acceleration
US8943058B1 (en) * 2009-12-14 2015-01-27 Teradata Us, Inc. Calculating aggregates of multiple combinations of a given set of columns
US8438335B2 (en) * 2010-09-28 2013-05-07 Intel Corporation Probe speculative address file

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5018063A (en) * 1988-12-05 1991-05-21 International Business Machines Corporation Method for reducing cross-interrogate delays in a multiprocessor system
US5680576A (en) * 1995-05-05 1997-10-21 Silicon Graphics, Inc. Directory-based coherence protocol allowing efficient dropping of clean-exclusive data

Also Published As

Publication number Publication date
US5923855A (en) 1999-07-13
CA2182841A1 (en) 1997-02-11
JPH0950400A (ja) 1997-02-18
DE69616903T2 (de) 2002-07-18
EP0758772A3 (de) 1998-02-11
EP0758772A2 (de) 1997-02-19
EP0758772B1 (de) 2001-11-14
CA2182841C (en) 2000-05-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee