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DE69418841D1 - Intelligente Prüfungsstrasse - Google Patents

Intelligente Prüfungsstrasse

Info

Publication number
DE69418841D1
DE69418841D1 DE69418841T DE69418841T DE69418841D1 DE 69418841 D1 DE69418841 D1 DE 69418841D1 DE 69418841 T DE69418841 T DE 69418841T DE 69418841 T DE69418841 T DE 69418841T DE 69418841 D1 DE69418841 D1 DE 69418841D1
Authority
DE
Germany
Prior art keywords
intelligent test
test lane
lane
intelligent
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69418841T
Other languages
English (en)
Other versions
DE69418841T2 (de
Inventor
Mitsugi Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69418841D1 publication Critical patent/DE69418841D1/de
Publication of DE69418841T2 publication Critical patent/DE69418841T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H10P74/23—
    • H10P74/00—

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE69418841T 1993-12-14 1994-12-14 Intelligente Prüfungsstrasse Expired - Fee Related DE69418841T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05313404A JP3099932B2 (ja) 1993-12-14 1993-12-14 インテリジェントテストラインシステム

Publications (2)

Publication Number Publication Date
DE69418841D1 true DE69418841D1 (de) 1999-07-08
DE69418841T2 DE69418841T2 (de) 1999-10-21

Family

ID=18040869

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69418841T Expired - Fee Related DE69418841T2 (de) 1993-12-14 1994-12-14 Intelligente Prüfungsstrasse

Country Status (5)

Country Link
US (1) US5635850A (de)
EP (1) EP0660385B1 (de)
JP (1) JP3099932B2 (de)
KR (1) KR0164247B1 (de)
DE (1) DE69418841T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716856A (en) * 1995-08-22 1998-02-10 Advanced Micro Devices, Inc. Arrangement and method for detecting sequential processing effects in manufacturing using predetermined sequences within runs
JP3691195B2 (ja) * 1997-02-13 2005-08-31 株式会社ルネサステクノロジ 半導体装置の製造方法
US6594598B1 (en) * 1997-10-08 2003-07-15 Matsushita Electronics Corporation Method for controlling production line
FR2790833B1 (fr) * 1999-03-08 2001-04-20 St Microelectronics Sa Procede de test statistique de circuits integres
JP3844912B2 (ja) * 1999-06-10 2006-11-15 富士通株式会社 半導体記憶装置の試験方法及び試験装置と半導体記憶装置
US6319737B1 (en) * 1999-08-10 2001-11-20 Advanced Micro Devices, Inc. Method and apparatus for characterizing a semiconductor device
WO2003044852A2 (en) * 2001-10-19 2003-05-30 Auburn University Estimating reliability of components for testing and quality optimization
US6915177B2 (en) * 2002-09-30 2005-07-05 Advanced Micro Devices, Inc. Comprehensive integrated lithographic process control system based on product design and yield feedback system
US7340359B2 (en) * 2005-05-02 2008-03-04 Optimaltest Ltd Augmenting semiconductor's devices quality and reliability
KR101250234B1 (ko) * 2005-12-29 2013-04-05 엘지디스플레이 주식회사 액정표시소자 검사시스템 및 방법, 이를 이용한액정표시소자 제조방법
US8299809B2 (en) * 2009-09-21 2012-10-30 International Business Machines Corporation In-line characterization of a device under test
JP5554750B2 (ja) * 2011-06-15 2014-07-23 富士通テレコムネットワークス株式会社 試験管理装置
JP6483373B2 (ja) * 2014-08-07 2019-03-13 株式会社東芝 生産支援システムおよび生産支援方法
JP5956094B1 (ja) * 2015-03-10 2016-07-20 三菱化学エンジニアリング株式会社 製造プロセスの解析方法
JP2018006603A (ja) * 2016-07-04 2018-01-11 富士通株式会社 システム、および試験決定方法
JP6716423B2 (ja) * 2016-10-26 2020-07-01 三菱ケミカルエンジニアリング株式会社 生産プロセスの解析方法
JP6481916B1 (ja) * 2018-06-26 2019-03-13 三菱ケミカルエンジニアリング株式会社 生産システム、生産方法及び制御装置
JP6549760B1 (ja) * 2018-06-26 2019-07-24 三菱ケミカルエンジニアリング株式会社 生産システム、生産方法、及び制御装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3344351A (en) * 1963-06-03 1967-09-26 Gen Instrument Corp Testing apparatus for a sequence of transistors and the like having a condition responsive marker
JPS60254626A (ja) * 1984-05-30 1985-12-16 Sharp Corp ウエハテスト方法
US4931722A (en) * 1985-11-07 1990-06-05 Control Data Corporation Flexible imbedded test system for VLSI circuits
JPH0616475B2 (ja) * 1987-04-03 1994-03-02 三菱電機株式会社 物品の製造システム及び物品の製造方法
US5093982A (en) * 1987-06-01 1992-03-10 Reliability Incorporated Automated burn-in system
US4985988A (en) * 1989-11-03 1991-01-22 Motorola, Inc. Method for assembling, testing, and packaging integrated circuits
JPH0425349A (ja) * 1990-05-21 1992-01-29 Mitsubishi Electric Corp 混成ロット編成方法及び装置
JP2925337B2 (ja) * 1990-12-27 1999-07-28 株式会社東芝 半導体装置
CA2073886A1 (en) * 1991-07-19 1993-01-20 Tatsuya Hashinaga Burn-in apparatus and method
CA2073916A1 (en) * 1991-07-19 1993-01-20 Tatsuya Hashinaga Burn-in apparatus and method
US5539652A (en) * 1995-02-07 1996-07-23 Hewlett-Packard Company Method for manufacturing test simulation in electronic circuit design

Also Published As

Publication number Publication date
US5635850A (en) 1997-06-03
JPH07167911A (ja) 1995-07-04
KR950019754A (ko) 1995-07-24
EP0660385A3 (de) 1996-06-05
JP3099932B2 (ja) 2000-10-16
DE69418841T2 (de) 1999-10-21
KR0164247B1 (ko) 1999-03-20
EP0660385A2 (de) 1995-06-28
EP0660385B1 (de) 1999-06-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee