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DE60335700D1 - Vorrichtung und Verfahren zum Ungültig-erklären von Befehlen in einer Befehlswarteschlange eines Pipelinemikroprozessors - Google Patents

Vorrichtung und Verfahren zum Ungültig-erklären von Befehlen in einer Befehlswarteschlange eines Pipelinemikroprozessors

Info

Publication number
DE60335700D1
DE60335700D1 DE60335700T DE60335700T DE60335700D1 DE 60335700 D1 DE60335700 D1 DE 60335700D1 DE 60335700 T DE60335700 T DE 60335700T DE 60335700 T DE60335700 T DE 60335700T DE 60335700 D1 DE60335700 D1 DE 60335700D1
Authority
DE
Germany
Prior art keywords
instruction queue
pipeline microprocessor
invalidating
instructions
invalidating instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60335700T
Other languages
English (en)
Inventor
Thomas Mcdonald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IP First LLC
Original Assignee
IP First LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IP First LLC filed Critical IP First LLC
Application granted granted Critical
Publication of DE60335700D1 publication Critical patent/DE60335700D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE60335700T 2003-01-14 2003-10-23 Vorrichtung und Verfahren zum Ungültig-erklären von Befehlen in einer Befehlswarteschlange eines Pipelinemikroprozessors Expired - Lifetime DE60335700D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44006303P 2003-01-14 2003-01-14
US10/632,224 US7143269B2 (en) 2003-01-14 2003-07-31 Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor

Publications (1)

Publication Number Publication Date
DE60335700D1 true DE60335700D1 (de) 2011-02-24

Family

ID=32600289

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60335700T Expired - Lifetime DE60335700D1 (de) 2003-01-14 2003-10-23 Vorrichtung und Verfahren zum Ungültig-erklären von Befehlen in einer Befehlswarteschlange eines Pipelinemikroprozessors

Country Status (3)

Country Link
US (1) US7143269B2 (de)
EP (1) EP1439458B1 (de)
DE (1) DE60335700D1 (de)

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US7237098B2 (en) * 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
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Also Published As

Publication number Publication date
EP1439458B1 (de) 2011-01-12
EP1439458A2 (de) 2004-07-21
US7143269B2 (en) 2006-11-28
EP1439458A3 (de) 2007-12-19
US20040139301A1 (en) 2004-07-15

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